psc.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Power and Sleep Controller (PSC) functions.
  4. *
  5. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  6. * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
  7. * Copyright (C) 2004 Texas Instruments.
  8. */
  9. #include <common.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/io.h>
  12. /*
  13. * The PSC manages three inputs to a "module" which may be a peripheral or
  14. * CPU. Those inputs are the module's: clock; reset signal; and sometimes
  15. * its power domain. For our purposes, we only care whether clock and power
  16. * are active, and the module is out of reset.
  17. *
  18. * DaVinci chips may include two separate power domains: "Always On" and "DSP".
  19. * Chips without a DSP generally have only one domain.
  20. *
  21. * The "Always On" power domain is always on when the chip is on, and is
  22. * powered by the VDD pins (on DM644X). The majority of DaVinci modules
  23. * lie within the "Always On" power domain.
  24. *
  25. * A separate domain called the "DSP" domain houses the C64x+ and other video
  26. * hardware such as VICP. In some chips, the "DSP" domain is not always on.
  27. * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
  28. */
  29. /* Works on Always On power domain only (no PD argument) */
  30. static void lpsc_transition(unsigned int id, unsigned int state)
  31. {
  32. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  33. #ifdef CONFIG_SOC_DA8XX
  34. struct davinci_psc_regs *psc_regs;
  35. #endif
  36. #ifndef CONFIG_SOC_DA8XX
  37. if (id >= DAVINCI_LPSC_GEM)
  38. return; /* Don't work on DSP Power Domain */
  39. mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
  40. mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
  41. ptstat = REG_P(PSC_PTSTAT);
  42. ptcmd = REG_P(PSC_PTCMD);
  43. #else
  44. if (id < DAVINCI_LPSC_PSC1_BASE) {
  45. if (id >= PSC_PSC0_MODULE_ID_CNT)
  46. return;
  47. psc_regs = davinci_psc0_regs;
  48. mdstat = &psc_regs->psc0.mdstat[id];
  49. mdctl = &psc_regs->psc0.mdctl[id];
  50. } else {
  51. id -= DAVINCI_LPSC_PSC1_BASE;
  52. if (id >= PSC_PSC1_MODULE_ID_CNT)
  53. return;
  54. psc_regs = davinci_psc1_regs;
  55. mdstat = &psc_regs->psc1.mdstat[id];
  56. mdctl = &psc_regs->psc1.mdctl[id];
  57. }
  58. ptstat = &psc_regs->ptstat;
  59. ptcmd = &psc_regs->ptcmd;
  60. #endif
  61. while (readl(ptstat) & 0x01)
  62. continue;
  63. if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
  64. return; /* Already in that state */
  65. writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
  66. switch (id) {
  67. #ifdef CONFIG_SOC_DM644X
  68. /* Special treatment for some modules as for sprue14 p.7.4.2 */
  69. case DAVINCI_LPSC_VPSSSLV:
  70. case DAVINCI_LPSC_EMAC:
  71. case DAVINCI_LPSC_EMAC_WRAPPER:
  72. case DAVINCI_LPSC_MDIO:
  73. case DAVINCI_LPSC_USB:
  74. case DAVINCI_LPSC_ATA:
  75. case DAVINCI_LPSC_VLYNQ:
  76. case DAVINCI_LPSC_UHPI:
  77. case DAVINCI_LPSC_DDR_EMIF:
  78. case DAVINCI_LPSC_AEMIF:
  79. case DAVINCI_LPSC_MMC_SD:
  80. case DAVINCI_LPSC_MEMSTICK:
  81. case DAVINCI_LPSC_McBSP:
  82. case DAVINCI_LPSC_GPIO:
  83. writel(readl(mdctl) | 0x200, mdctl);
  84. break;
  85. #endif
  86. }
  87. writel(0x01, ptcmd);
  88. while (readl(ptstat) & 0x01)
  89. continue;
  90. while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
  91. continue;
  92. }
  93. void lpsc_on(unsigned int id)
  94. {
  95. lpsc_transition(id, 0x03);
  96. }
  97. void lpsc_syncreset(unsigned int id)
  98. {
  99. lpsc_transition(id, 0x01);
  100. }
  101. void lpsc_disable(unsigned int id)
  102. {
  103. lpsc_transition(id, 0x0);
  104. }
  105. /* Not all DaVinci chips have a DSP power domain. */
  106. #ifdef CONFIG_SOC_DM644X
  107. /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
  108. #if !defined(CONFIG_SYS_USE_DSPLINK)
  109. void dsp_on(void)
  110. {
  111. int i;
  112. if (REG(PSC_PDSTAT1) & 0x1f)
  113. return; /* Already on */
  114. REG(PSC_GBLCTL) |= 0x01;
  115. REG(PSC_PDCTL1) |= 0x01;
  116. REG(PSC_PDCTL1) &= ~0x100;
  117. REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
  118. REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
  119. REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
  120. REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
  121. REG(PSC_PTCMD) = 0x02;
  122. for (i = 0; i < 100; i++) {
  123. if (REG(PSC_EPCPR) & 0x02)
  124. break;
  125. }
  126. REG(PSC_CHP_SHRTSW) = 0x01;
  127. REG(PSC_PDCTL1) |= 0x100;
  128. REG(PSC_EPCCR) = 0x02;
  129. for (i = 0; i < 100; i++) {
  130. if (!(REG(PSC_PTSTAT) & 0x02))
  131. break;
  132. }
  133. REG(PSC_GBLCTL) &= ~0x1f;
  134. }
  135. #endif /* CONFIG_SYS_USE_DSPLINK */
  136. #endif /* have a DSP */