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arch
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asm
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arch-vf610
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ddrmc-vf610.h

ddrmc-vf610.h 1.3 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * Copyright (C) 2015
    4. 

  4.  * Toradex, Inc.
    5. 

  5.  *
    6. 

  6.  * Authors: Stefan Agner
    7. 

  7.  *          Sanchayan Maity
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __ASM_ARCH_VF610_DDRMC_H
    11. 

  11. #define __ASM_ARCH_VF610_DDRMC_H
    12. 

  12. 

  13. struct ddr3_jedec_timings {
    14. 

  14. 	u8 tinit;
    15. 

  15. 	u32 trst_pwron;
    16. 

  16. 	u32 cke_inactive;
    17. 

  17. 	u8 wrlat;
    18. 

  18. 	u8 caslat_lin;
    19. 

  19. 	u8 trc;
    20. 

  20. 	u8 trrd;
    21. 

  21. 	u8 tccd;
    22. 

  22. 	u8 tbst_int_interval;
    23. 

  23. 	u8 tfaw;
    24. 

  24. 	u8 trp;
    25. 

  25. 	u8 twtr;
    26. 

  26. 	u8 tras_min;
    27. 

  27. 	u8 tmrd;
    28. 

  28. 	u8 trtp;
    29. 

  29. 	u32 tras_max;
    30. 

  30. 	u8 tmod;
    31. 

  31. 	u8 tckesr;
    32. 

  32. 	u8 tcke;
    33. 

  33. 	u8 trcd_int;
    34. 

  34. 	u8 tras_lockout;
    35. 

  35. 	u8 tdal;
    36. 

  36. 	u8 bstlen;
    37. 

  37. 	u16 tdll;
    38. 

  38. 	u8 trp_ab;
    39. 

  39. 	u16 tref;
    40. 

  40. 	u8 trfc;
    41. 

  41. 	u16 tref_int;
    42. 

  42. 	u8 tpdex;
    43. 

  43. 	u8 txpdll;
    44. 

  44. 	u8 txsnr;
    45. 

  45. 	u16 txsr;
    46. 

  46. 	u8 cksrx;
    47. 

  47. 	u8 cksre;
    48. 

  48. 	u8 freq_chg_en;
    49. 

  49. 	u16 zqcl;
    50. 

  50. 	u16 zqinit;
    51. 

  51. 	u8 zqcs;
    52. 

  52. 	u8 ref_per_zq;
    53. 

  53. 	u8 zqcs_rotate;
    54. 

  54. 	u8 aprebit;
    55. 

  55. 	u8 cmd_age_cnt;
    56. 

  56. 	u8 age_cnt;
    57. 

  57. 	u8 q_fullness;
    58. 

  58. 	u8 odt_rd_mapcs0;
    59. 

  59. 	u8 odt_wr_mapcs0;
    60. 

  60. 	u8 wlmrd;
    61. 

  61. 	u8 wldqsen;
    62. 

  62. };
    63. 

  63. 

  64. struct ddrmc_cr_setting {
    65. 

  65. 	u32	setting;
    66. 

  66. 	int	cr_rnum; /* CR register ; -1 for last entry */
    67. 

  67. };
    68. 

  68. 

  69. struct ddrmc_phy_setting {
    70. 

  70. 	u32	setting;
    71. 

  71. 	int	phy_rnum; /* PHY register ; -1 for last entry */
    72. 

  72. };
    73. 

  73. 

  74. void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
    75. 

  75. void ddrmc_phy_init(void);
    76. 

  76. void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
    77. 

  77. 			  struct ddrmc_cr_setting *board_cr_settings,
    78. 

  78. 			  struct ddrmc_phy_setting *board_phy_settings,
    79. 

  79. 			  int col_diff, int row_diff);
    80. 

  80. 

  81. #endif
    82.