mc_rgm_regs.h 994 B

123456789101112131415161718192021222324252627282930
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2015, Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
  6. #define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
  7. #define MC_RGM_DES (MC_RGM_BASE_ADDR)
  8. #define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
  9. #define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
  10. #define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
  11. #define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
  12. #define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
  13. #define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
  14. #define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
  15. #define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
  16. #define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
  17. #define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
  18. /* function reset sources mask */
  19. #define F_SWT4 0x8000
  20. #define F_JTAG 0x400
  21. #define F_FCCU_SOFT 0x40
  22. #define F_FCCU_HARD 0x20
  23. #define F_SOFT_FUNC 0x8
  24. #define F_ST_DONE 0x4
  25. #define F_EXT_RST 0x1
  26. #endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */