ps7_init_gpl.h 4.2 KB

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  1. /******************************************************************************
  2. *
  3. * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>
  17. *
  18. *
  19. *******************************************************************************/
  20. /****************************************************************************/
  21. /**
  22. *
  23. * @file ps7_init.h
  24. *
  25. * This file can be included in FSBL code
  26. * to get prototype of ps7_init() function
  27. * and error codes
  28. *
  29. *****************************************************************************/
  30. #ifdef __cplusplus
  31. extern "C" {
  32. #endif
  33. //typedef unsigned int u32;
  34. /** do we need to make this name more unique ? **/
  35. //extern u32 ps7_init_data[];
  36. extern unsigned long * ps7_ddr_init_data;
  37. extern unsigned long * ps7_mio_init_data;
  38. extern unsigned long * ps7_pll_init_data;
  39. extern unsigned long * ps7_clock_init_data;
  40. extern unsigned long * ps7_peripherals_init_data;
  41. #define OPCODE_EXIT 0U
  42. #define OPCODE_CLEAR 1U
  43. #define OPCODE_WRITE 2U
  44. #define OPCODE_MASKWRITE 3U
  45. #define OPCODE_MASKPOLL 4U
  46. #define OPCODE_MASKDELAY 5U
  47. #define NEW_PS7_ERR_CODE 1
  48. /* Encode number of arguments in last nibble */
  49. #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
  50. #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
  51. #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
  52. #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
  53. #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
  54. #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
  55. /* Returns codes of PS7_Init */
  56. #define PS7_INIT_SUCCESS (0) // 0 is success in good old C
  57. #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
  58. #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
  59. #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
  60. #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
  61. #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
  62. /* Silicon Versions */
  63. #define PCW_SILICON_VERSION_1 0
  64. #define PCW_SILICON_VERSION_2 1
  65. #define PCW_SILICON_VERSION_3 2
  66. /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
  67. #define PS7_POST_CONFIG
  68. /* Freq of all peripherals */
  69. #define APU_FREQ 666666687
  70. #define DDR_FREQ 533333374
  71. #define DCI_FREQ 10158731
  72. #define QSPI_FREQ 200000000
  73. #define SMC_FREQ 10000000
  74. #define ENET0_FREQ 125000000
  75. #define ENET1_FREQ 10000000
  76. #define USB0_FREQ 60000000
  77. #define USB1_FREQ 60000000
  78. #define SDIO_FREQ 50000000
  79. #define UART_FREQ 50000000
  80. #define SPI_FREQ 10000000
  81. #define I2C_FREQ 111111115
  82. #define WDT_FREQ 111111115
  83. #define TTC_FREQ 50000000
  84. #define CAN_FREQ 10000000
  85. #define PCAP_FREQ 200000000
  86. #define TPIU_FREQ 200000000
  87. #define FPGA0_FREQ 100000000
  88. #define FPGA1_FREQ 142857132
  89. #define FPGA2_FREQ 50000000
  90. #define FPGA3_FREQ 50000000
  91. /* For delay calculation using global registers*/
  92. #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
  93. #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
  94. #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
  95. #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
  96. int ps7_config( unsigned long*);
  97. int ps7_init();
  98. int ps7_post_config();
  99. int ps7_debug();
  100. char* getPS7MessageInfo(unsigned key);
  101. void perf_start_clock(void);
  102. void perf_disable_clock(void);
  103. void perf_reset_clock(void);
  104. void perf_reset_and_start_timer();
  105. int get_number_of_cycles_for_delay(unsigned int delay);
  106. #ifdef __cplusplus
  107. }
  108. #endif