board.c 3.1 KB

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  1. /*
  2. * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <fdtdec.h>
  8. #include <fpga.h>
  9. #include <mmc.h>
  10. #include <netdev.h>
  11. #include <zynqpl.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/sys_proto.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  16. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  17. static xilinx_desc fpga;
  18. /* It can be done differently */
  19. static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  20. static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  21. static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  22. static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  23. static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  24. static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  25. static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  26. #endif
  27. int board_init(void)
  28. {
  29. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  30. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  31. u32 idcode;
  32. idcode = zynq_slcr_get_idcode();
  33. switch (idcode) {
  34. case XILINX_ZYNQ_7010:
  35. fpga = fpga010;
  36. break;
  37. case XILINX_ZYNQ_7015:
  38. fpga = fpga015;
  39. break;
  40. case XILINX_ZYNQ_7020:
  41. fpga = fpga020;
  42. break;
  43. case XILINX_ZYNQ_7030:
  44. fpga = fpga030;
  45. break;
  46. case XILINX_ZYNQ_7035:
  47. fpga = fpga035;
  48. break;
  49. case XILINX_ZYNQ_7045:
  50. fpga = fpga045;
  51. break;
  52. case XILINX_ZYNQ_7100:
  53. fpga = fpga100;
  54. break;
  55. }
  56. #endif
  57. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  58. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  59. fpga_init();
  60. fpga_add(fpga_xilinx, &fpga);
  61. #endif
  62. return 0;
  63. }
  64. int board_late_init(void)
  65. {
  66. switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  67. case ZYNQ_BM_NOR:
  68. setenv("modeboot", "norboot");
  69. break;
  70. case ZYNQ_BM_SD:
  71. setenv("modeboot", "sdboot");
  72. break;
  73. case ZYNQ_BM_JTAG:
  74. setenv("modeboot", "jtagboot");
  75. break;
  76. default:
  77. setenv("modeboot", "");
  78. break;
  79. }
  80. return 0;
  81. }
  82. #ifdef CONFIG_DISPLAY_BOARDINFO
  83. int checkboard(void)
  84. {
  85. puts("Board:\tXilinx Zynq\n");
  86. return 0;
  87. }
  88. #endif
  89. int board_eth_init(bd_t *bis)
  90. {
  91. u32 ret = 0;
  92. #ifdef CONFIG_XILINX_AXIEMAC
  93. ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
  94. XILINX_AXIDMA_BASEADDR);
  95. #endif
  96. #ifdef CONFIG_XILINX_EMACLITE
  97. u32 txpp = 0;
  98. u32 rxpp = 0;
  99. # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
  100. txpp = 1;
  101. # endif
  102. # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
  103. rxpp = 1;
  104. # endif
  105. ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
  106. txpp, rxpp);
  107. #endif
  108. return ret;
  109. }
  110. int dram_init(void)
  111. {
  112. #if CONFIG_IS_ENABLED(OF_CONTROL)
  113. int node;
  114. fdt_addr_t addr;
  115. fdt_size_t size;
  116. const void *blob = gd->fdt_blob;
  117. node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
  118. "memory", 7);
  119. if (node == -FDT_ERR_NOTFOUND) {
  120. debug("ZYNQ DRAM: Can't get memory node\n");
  121. return -1;
  122. }
  123. addr = fdtdec_get_addr_size(blob, node, "reg", &size);
  124. if (addr == FDT_ADDR_T_NONE || size == 0) {
  125. debug("ZYNQ DRAM: Can't get base address or size\n");
  126. return -1;
  127. }
  128. gd->ram_size = size;
  129. #else
  130. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  131. #endif
  132. zynq_ddrc_init();
  133. return 0;
  134. }