cds_via.c 3.0 KB

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  1. /*
  2. * Copyright 2006 Freescale Semiconductor.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <pci.h>
  8. /* Config the VIA chip */
  9. void mpc85xx_config_via(struct pci_controller *hose,
  10. pci_dev_t dev, struct pci_config_table *tab)
  11. {
  12. pci_dev_t bridge;
  13. unsigned int cmdstat;
  14. /* Enable USB and IDE functions */
  15. pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
  16. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
  17. cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
  18. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
  19. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  20. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  21. /*
  22. * Force the backplane P2P bridge to have a window
  23. * open from 0x00000000-0x00001fff in PCI I/O space.
  24. * This allows legacy I/O (i8259, etc) on the VIA
  25. * southbridge to be accessed.
  26. */
  27. bridge = PCI_BDF(0,BRIDGE_ID,0);
  28. pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
  29. pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
  30. pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
  31. pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
  32. }
  33. /* Function 1, IDE */
  34. void mpc85xx_config_via_usbide(struct pci_controller *hose,
  35. pci_dev_t dev, struct pci_config_table *tab)
  36. {
  37. pciauto_config_device(hose, dev);
  38. /*
  39. * Since the P2P window was forced to cover the fixed
  40. * legacy I/O addresses, it is necessary to manually
  41. * place the base addresses for the IDE and USB functions
  42. * within this window.
  43. */
  44. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
  45. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
  46. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
  47. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
  48. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
  49. }
  50. /* Function 2, USB ports 0-1 */
  51. void mpc85xx_config_via_usb(struct pci_controller *hose,
  52. pci_dev_t dev, struct pci_config_table *tab)
  53. {
  54. pciauto_config_device(hose, dev);
  55. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
  56. }
  57. /* Function 3, USB ports 2-3 */
  58. void mpc85xx_config_via_usb2(struct pci_controller *hose,
  59. pci_dev_t dev, struct pci_config_table *tab)
  60. {
  61. pciauto_config_device(hose, dev);
  62. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
  63. }
  64. /* Function 5, Power Management */
  65. void mpc85xx_config_via_power(struct pci_controller *hose,
  66. pci_dev_t dev, struct pci_config_table *tab)
  67. {
  68. pciauto_config_device(hose, dev);
  69. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
  70. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
  71. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
  72. }
  73. /* Function 6, AC97 Interface */
  74. void mpc85xx_config_via_ac97(struct pci_controller *hose,
  75. pci_dev_t dev, struct pci_config_table *tab)
  76. {
  77. pciauto_config_device(hose, dev);
  78. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
  79. }