at91sam9261ek.c 7.5 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian@popies.net>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91sam9261.h>
  11. #include <asm/arch/at91sam9261_matrix.h>
  12. #include <asm/arch/at91sam9_smc.h>
  13. #include <asm/arch/at91_common.h>
  14. #include <asm/arch/at91_pmc.h>
  15. #include <asm/arch/at91_rstc.h>
  16. #include <asm/arch/clk.h>
  17. #include <asm/arch/gpio.h>
  18. #include <lcd.h>
  19. #include <atmel_lcdc.h>
  20. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  21. #include <net.h>
  22. #include <netdev.h>
  23. #endif
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /* ------------------------------------------------------------------------- */
  26. /*
  27. * Miscelaneous platform dependent initialisations
  28. */
  29. #ifdef CONFIG_CMD_NAND
  30. static void at91sam9261ek_nand_hw_init(void)
  31. {
  32. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  33. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  34. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  35. unsigned long csa;
  36. /* Enable CS3 */
  37. csa = readl(&matrix->ebicsa);
  38. csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  39. writel(csa, &matrix->ebicsa);
  40. /* Configure SMC CS3 for NAND/SmartMedia */
  41. #ifdef CONFIG_AT91SAM9G10EK
  42. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  43. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  44. &smc->cs[3].setup);
  45. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
  46. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
  47. &smc->cs[3].pulse);
  48. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  49. &smc->cs[3].cycle);
  50. #else
  51. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  52. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  53. &smc->cs[3].setup);
  54. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  55. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  56. &smc->cs[3].pulse);
  57. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  58. &smc->cs[3].cycle);
  59. #endif
  60. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  61. AT91_SMC_MODE_EXNW_DISABLE |
  62. #ifdef CONFIG_SYS_NAND_DBW_16
  63. AT91_SMC_MODE_DBW_16 |
  64. #else /* CONFIG_SYS_NAND_DBW_8 */
  65. AT91_SMC_MODE_DBW_8 |
  66. #endif
  67. AT91_SMC_MODE_TDF_CYCLE(2),
  68. &smc->cs[3].mode);
  69. writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  70. /* Configure RDY/BSY */
  71. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  72. /* Enable NandFlash */
  73. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  74. at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
  75. at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
  76. }
  77. #endif
  78. #ifdef CONFIG_DRIVER_DM9000
  79. static void at91sam9261ek_dm9000_hw_init(void)
  80. {
  81. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  82. /* Configure SMC CS2 for DM9000 */
  83. #ifdef CONFIG_AT91SAM9G10EK
  84. writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  85. AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
  86. &smc->cs[2].setup);
  87. writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
  88. AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
  89. &smc->cs[2].pulse);
  90. writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
  91. &smc->cs[2].cycle);
  92. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  93. AT91_SMC_MODE_EXNW_DISABLE |
  94. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  95. AT91_SMC_MODE_TDF_CYCLE(1),
  96. &smc->cs[2].mode);
  97. #else
  98. writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  99. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  100. &smc->cs[2].setup);
  101. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
  102. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
  103. &smc->cs[2].pulse);
  104. writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
  105. &smc->cs[2].cycle);
  106. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  107. AT91_SMC_MODE_EXNW_DISABLE |
  108. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  109. AT91_SMC_MODE_TDF_CYCLE(1),
  110. &smc->cs[2].mode);
  111. #endif
  112. /* Configure Reset signal as output */
  113. at91_set_gpio_output(AT91_PIN_PC10, 0);
  114. /* Configure Interrupt pin as input, no pull-up */
  115. at91_set_gpio_input(AT91_PIN_PC11, 0);
  116. }
  117. #endif
  118. #ifdef CONFIG_LCD
  119. vidinfo_t panel_info = {
  120. .vl_col = 240,
  121. .vl_row = 320,
  122. .vl_clk = 4965000,
  123. .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
  124. ATMEL_LCDC_INVFRAME_INVERTED,
  125. .vl_bpix = 3,
  126. .vl_tft = 1,
  127. .vl_hsync_len = 5,
  128. .vl_left_margin = 1,
  129. .vl_right_margin = 33,
  130. .vl_vsync_len = 1,
  131. .vl_upper_margin = 1,
  132. .vl_lower_margin = 0,
  133. .mmio = ATMEL_BASE_LCDC,
  134. };
  135. void lcd_enable(void)
  136. {
  137. at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
  138. }
  139. void lcd_disable(void)
  140. {
  141. at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
  142. }
  143. static void at91sam9261ek_lcd_hw_init(void)
  144. {
  145. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  146. at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
  147. at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
  148. at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
  149. at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
  150. at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
  151. at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
  152. at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
  153. at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
  154. at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
  155. at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
  156. at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
  157. at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
  158. at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
  159. at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
  160. at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
  161. at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
  162. at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
  163. at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
  164. at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
  165. at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
  166. at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
  167. at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
  168. writel(AT91_PMC_HCK1, &pmc->scer);
  169. /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
  170. #ifdef CONFIG_AT91SAM9261EK
  171. gd->fb_base = ATMEL_BASE_SRAM;
  172. #endif
  173. }
  174. #ifdef CONFIG_LCD_INFO
  175. #include <nand.h>
  176. #include <version.h>
  177. void lcd_show_board_info(void)
  178. {
  179. ulong dram_size, nand_size;
  180. int i;
  181. char temp[32];
  182. lcd_printf ("%s\n", U_BOOT_VERSION);
  183. lcd_printf ("(C) 2008 ATMEL Corp\n");
  184. lcd_printf ("at91support@atmel.com\n");
  185. lcd_printf ("%s CPU at %s MHz\n",
  186. ATMEL_CPU_NAME,
  187. strmhz(temp, get_cpu_clk_rate()));
  188. dram_size = 0;
  189. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  190. dram_size += gd->bd->bi_dram[i].size;
  191. nand_size = 0;
  192. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  193. nand_size += nand_info[i].size;
  194. lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
  195. dram_size >> 20,
  196. nand_size >> 20 );
  197. }
  198. #endif /* CONFIG_LCD_INFO */
  199. #endif
  200. int board_init(void)
  201. {
  202. #ifdef CONFIG_AT91SAM9G10EK
  203. /* arch number of AT91SAM9G10EK-Board */
  204. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
  205. #else
  206. /* arch number of AT91SAM9261EK-Board */
  207. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
  208. #endif
  209. /* adress of boot parameters */
  210. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  211. at91_seriald_hw_init();
  212. #ifdef CONFIG_CMD_NAND
  213. at91sam9261ek_nand_hw_init();
  214. #endif
  215. #ifdef CONFIG_HAS_DATAFLASH
  216. at91_spi0_hw_init(1 << 0);
  217. #endif
  218. #ifdef CONFIG_DRIVER_DM9000
  219. at91sam9261ek_dm9000_hw_init();
  220. #endif
  221. #ifdef CONFIG_LCD
  222. at91sam9261ek_lcd_hw_init();
  223. #endif
  224. return 0;
  225. }
  226. #ifdef CONFIG_DRIVER_DM9000
  227. int board_eth_init(bd_t *bis)
  228. {
  229. return dm9000_initialize(bis);
  230. }
  231. #endif
  232. int dram_init(void)
  233. {
  234. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  235. CONFIG_SYS_SDRAM_SIZE);
  236. return 0;
  237. }
  238. #ifdef CONFIG_RESET_PHY_R
  239. void reset_phy(void)
  240. {
  241. #ifdef CONFIG_DRIVER_DM9000
  242. /*
  243. * Initialize ethernet HW addr prior to starting Linux,
  244. * needed for nfsroot
  245. */
  246. eth_init();
  247. #endif
  248. }
  249. #endif