start.S 6.6 KB

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  1. /*
  2. * Startup Code for MIPS32 CPU-core
  3. *
  4. * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <asm-offsets.h>
  9. #include <config.h>
  10. #include <asm/asm.h>
  11. #include <asm/regdef.h>
  12. #include <asm/mipsregs.h>
  13. #ifndef CONFIG_SYS_MIPS_CACHE_MODE
  14. #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
  15. #endif
  16. #ifndef CONFIG_SYS_INIT_SP_ADDR
  17. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
  18. CONFIG_SYS_INIT_SP_OFFSET)
  19. #endif
  20. #ifdef CONFIG_32BIT
  21. # define MIPS_RELOC 3
  22. # define STATUS_SET 0
  23. #endif
  24. #ifdef CONFIG_64BIT
  25. # ifdef CONFIG_SYS_LITTLE_ENDIAN
  26. # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  27. (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
  28. # else
  29. # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  30. ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
  31. # endif
  32. # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
  33. # define STATUS_SET ST0_KX
  34. #endif
  35. /*
  36. * For the moment disable interrupts, mark the kernel mode and
  37. * set ST0_KX so that the CPU does not spit fire when using
  38. * 64-bit addresses.
  39. */
  40. .macro setup_c0_status set clr
  41. .set push
  42. mfc0 t0, CP0_STATUS
  43. or t0, ST0_CU0 | \set | 0x1f | \clr
  44. xor t0, 0x1f | \clr
  45. mtc0 t0, CP0_STATUS
  46. .set noreorder
  47. sll zero, 3 # ehb
  48. .set pop
  49. .endm
  50. .set noreorder
  51. .globl _start
  52. .text
  53. _start:
  54. /* U-boot entry point */
  55. b reset
  56. nop
  57. .org 0x10
  58. #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
  59. /*
  60. * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
  61. * access external NOR flashes. If the board boots from NOR flash the
  62. * internal BootROM does a blind read at address 0xB0000010 to read the
  63. * initial configuration for that EBU in order to access the flash
  64. * device with correct parameters. This config option is board-specific.
  65. */
  66. .word CONFIG_SYS_XWAY_EBU_BOOTCFG
  67. .word 0x0
  68. #elif defined(CONFIG_MALTA)
  69. /*
  70. * Linux expects the Board ID here.
  71. */
  72. .word 0x00000420 # 0x420 (Malta Board with CoreLV)
  73. .word 0x00000000
  74. #endif
  75. .org 0x200
  76. /* TLB refill, 32 bit task */
  77. 1: b 1b
  78. nop
  79. .org 0x280
  80. /* XTLB refill, 64 bit task */
  81. 1: b 1b
  82. nop
  83. .org 0x300
  84. /* Cache error exception */
  85. 1: b 1b
  86. nop
  87. .org 0x380
  88. /* General exception */
  89. 1: b 1b
  90. nop
  91. .org 0x400
  92. /* Catch interrupt exceptions */
  93. 1: b 1b
  94. nop
  95. .org 0x480
  96. /* EJTAG debug exception */
  97. 1: b 1b
  98. nop
  99. .align 4
  100. reset:
  101. /* Clear watch registers */
  102. MTC0 zero, CP0_WATCHLO
  103. MTC0 zero, CP0_WATCHHI
  104. /* WP(Watch Pending), SW0/1 should be cleared */
  105. mtc0 zero, CP0_CAUSE
  106. setup_c0_status STATUS_SET 0
  107. /* Init Timer */
  108. mtc0 zero, CP0_COUNT
  109. mtc0 zero, CP0_COMPARE
  110. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  111. /* CONFIG0 register */
  112. li t0, CONF_CM_UNCACHED
  113. mtc0 t0, CP0_CONFIG
  114. #endif
  115. /*
  116. * Initialize $gp, force pointer sized alignment of bal instruction to
  117. * forbid the compiler to put nop's between bal and _gp. This is
  118. * required to keep _gp and ra aligned to 8 byte.
  119. */
  120. .align PTRLOG
  121. bal 1f
  122. nop
  123. PTR _gp
  124. 1:
  125. PTR_L gp, 0(ra)
  126. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  127. /* Initialize any external memory */
  128. PTR_LA t9, lowlevel_init
  129. jalr t9
  130. nop
  131. /* Initialize caches... */
  132. PTR_LA t9, mips_cache_reset
  133. jalr t9
  134. nop
  135. /* ... and enable them */
  136. li t0, CONFIG_SYS_MIPS_CACHE_MODE
  137. mtc0 t0, CP0_CONFIG
  138. #endif
  139. /* Set up temporary stack */
  140. PTR_LI t0, -16
  141. PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
  142. and sp, t1, t0 # force 16 byte alignment
  143. PTR_SUB sp, sp, GD_SIZE # reserve space for gd
  144. and sp, sp, t0 # force 16 byte alignment
  145. move k0, sp # save gd pointer
  146. #ifdef CONFIG_SYS_MALLOC_F_LEN
  147. PTR_LI t2, CONFIG_SYS_MALLOC_F_LEN
  148. PTR_SUB sp, sp, t2 # reserve space for early malloc
  149. and sp, sp, t0 # force 16 byte alignment
  150. #endif
  151. move fp, sp
  152. /* Clear gd */
  153. move t0, k0
  154. 1:
  155. sw zero, 0(t0)
  156. blt t0, t1, 1b
  157. PTR_ADDI t0, 4
  158. #ifdef CONFIG_SYS_MALLOC_F_LEN
  159. PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
  160. sw sp, 0(t0)
  161. #endif
  162. PTR_LA t9, board_init_f
  163. jr t9
  164. move ra, zero
  165. /*
  166. * void relocate_code (addr_sp, gd, addr_moni)
  167. *
  168. * This "function" does not return, instead it continues in RAM
  169. * after relocating the monitor code.
  170. *
  171. * a0 = addr_sp
  172. * a1 = gd
  173. * a2 = destination address
  174. */
  175. .globl relocate_code
  176. .ent relocate_code
  177. relocate_code:
  178. move sp, a0 # set new stack pointer
  179. move fp, sp
  180. move s0, a1 # save gd in s0
  181. move s2, a2 # save destination address in s2
  182. PTR_LI t0, CONFIG_SYS_MONITOR_BASE
  183. PTR_SUB s1, s2, t0 # s1 <-- relocation offset
  184. PTR_LA t3, in_ram
  185. PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
  186. move t1, a2
  187. PTR_ADD gp, s1 # adjust gp
  188. /*
  189. * t0 = source address
  190. * t1 = target address
  191. * t2 = source end address
  192. */
  193. 1:
  194. lw t3, 0(t0)
  195. sw t3, 0(t1)
  196. PTR_ADDU t0, 4
  197. blt t0, t2, 1b
  198. PTR_ADDU t1, 4
  199. /* If caches were enabled, we would have to flush them here. */
  200. PTR_SUB a1, t1, s2 # a1 <-- size
  201. PTR_LA t9, flush_cache
  202. jalr t9
  203. move a0, s2 # a0 <-- destination address
  204. /* Jump to where we've relocated ourselves */
  205. PTR_ADDI t0, s2, in_ram - _start
  206. jr t0
  207. nop
  208. PTR __rel_dyn_end
  209. PTR __rel_dyn_start
  210. PTR __image_copy_end
  211. PTR _GLOBAL_OFFSET_TABLE_
  212. PTR num_got_entries
  213. in_ram:
  214. /*
  215. * Now we want to update GOT.
  216. *
  217. * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
  218. * generated by GNU ld. Skip these reserved entries from relocation.
  219. */
  220. PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
  221. PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
  222. PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
  223. PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries
  224. PTR_LI t2, 2
  225. 1:
  226. PTR_L t1, 0(t8)
  227. beqz t1, 2f
  228. PTR_ADD t1, s1
  229. PTR_S t1, 0(t8)
  230. 2:
  231. PTR_ADDI t2, 1
  232. blt t2, t3, 1b
  233. PTR_ADDI t8, PTRSIZE
  234. /* Update dynamic relocations */
  235. PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
  236. PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
  237. b 2f # skip first reserved entry
  238. PTR_ADDI t1, 2 * PTRSIZE
  239. 1:
  240. lw t8, -4(t1) # t8 <-- relocation info
  241. PTR_LI t3, MIPS_RELOC
  242. bne t8, t3, 2f # skip non-MIPS_RELOC entries
  243. nop
  244. PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
  245. PTR_L t8, 0(t3) # t8 <-- original pointer
  246. PTR_ADD t8, s1 # t8 <-- adjusted pointer
  247. PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
  248. PTR_S t8, 0(t3)
  249. 2:
  250. blt t1, t2, 1b
  251. PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
  252. /*
  253. * Clear BSS
  254. *
  255. * GOT is now relocated. Thus __bss_start and __bss_end can be
  256. * accessed directly via $gp.
  257. */
  258. PTR_LA t1, __bss_start # t1 <-- __bss_start
  259. PTR_LA t2, __bss_end # t2 <-- __bss_end
  260. 1:
  261. PTR_S zero, 0(t1)
  262. blt t1, t2, 1b
  263. PTR_ADDI t1, PTRSIZE
  264. move a0, s0 # a0 <-- gd
  265. move a1, s2
  266. PTR_LA t9, board_init_r
  267. jr t9
  268. move ra, zero
  269. .end relocate_code