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arch
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arm
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mach-stm32mp
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include
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mach
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stm32.h

stm32.h 1.9 KB
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  1. /*
    2. 

  2.  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+	BSD-3-Clause
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _MACH_STM32_H_
    8. 

  8. #define _MACH_STM32_H_
    9. 

  9. 

  10. /*
    11. 

  11.  * Peripheral memory map
    12. 

  12.  * only address used before device tree parsing
    13. 

  13.  */
    14. 

  14. #define STM32_RCC_BASE			0x50000000
    15. 

  15. #define STM32_PWR_BASE			0x50001000
    16. 

  16. #define STM32_DBGMCU_BASE		0x50081000
    17. 

  17. #define STM32_TZC_BASE			0x5C006000
    18. 

  18. #define STM32_ETZPC_BASE		0x5C007000
    19. 

  19. #define STM32_TAMP_BASE			0x5C00A000
    20. 

  20. 

  21. #define STM32_SYSRAM_BASE		0x2FFC0000
    22. 

  22. #define STM32_SYSRAM_SIZE		SZ_256K
    23. 

  23. 

  24. #define STM32_DDR_BASE			0xC0000000
    25. 

  25. #define STM32_DDR_SIZE			SZ_1G
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. 

  29. /*
    30. 

  30.  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
    31. 

  31.  * - boot device = bit 8:4
    32. 

  32.  * - boot instance = bit 3:0
    33. 

  33.  */
    34. 

  34. #define BOOT_TYPE_MASK		0xF0
    35. 

  35. #define BOOT_TYPE_SHIFT		4
    36. 

  36. #define BOOT_INSTANCE_MASK	0x0F
    37. 

  37. #define BOOT_INSTANCE_SHIFT	0
    38. 

  38. 

  39. enum boot_device {
    40. 

  40. 	BOOT_FLASH_SD = 0x10,
    41. 

  41. 	BOOT_FLASH_SD_1 = 0x11,
    42. 

  42. 	BOOT_FLASH_SD_2 = 0x12,
    43. 

  43. 	BOOT_FLASH_SD_3 = 0x13,
    44. 

  44. 

  45. 	BOOT_FLASH_EMMC = 0x20,
    46. 

  46. 	BOOT_FLASH_EMMC_1 = 0x21,
    47. 

  47. 	BOOT_FLASH_EMMC_2 = 0x22,
    48. 

  48. 	BOOT_FLASH_EMMC_3 = 0x23,
    49. 

  49. 

  50. 	BOOT_FLASH_NAND = 0x30,
    51. 

  51. 	BOOT_FLASH_NAND_FMC = 0x31,
    52. 

  52. 

  53. 	BOOT_FLASH_NOR = 0x40,
    54. 

  54. 	BOOT_FLASH_NOR_QSPI = 0x41,
    55. 

  55. 

  56. 	BOOT_SERIAL_UART = 0x50,
    57. 

  57. 	BOOT_SERIAL_UART_1 = 0x51,
    58. 

  58. 	BOOT_SERIAL_UART_2 = 0x52,
    59. 

  59. 	BOOT_SERIAL_UART_3 = 0x53,
    60. 

  60. 	BOOT_SERIAL_UART_4 = 0x54,
    61. 

  61. 	BOOT_SERIAL_UART_5 = 0x55,
    62. 

  62. 	BOOT_SERIAL_UART_6 = 0x56,
    63. 

  63. 	BOOT_SERIAL_UART_7 = 0x57,
    64. 

  64. 	BOOT_SERIAL_UART_8 = 0x58,
    65. 

  65. 

  66. 	BOOT_SERIAL_USB = 0x60,
    67. 

  67. 	BOOT_SERIAL_USB_OTG = 0x62,
    68. 

  68. };
    69. 

  69. 

  70. /* TAMP registers */
    71. 

  71. #define TAMP_BACKUP_REGISTER(x)		(STM32_TAMP_BASE + 0x100 + 4 * x)
    72. 

  72. #define TAMP_BOOT_CONTEXT		TAMP_BACKUP_REGISTER(20)
    73. 

  73. 

  74. #define TAMP_BOOT_MODE_MASK		GENMASK(15, 8)
    75. 

  75. #define TAMP_BOOT_MODE_SHIFT		8
    76. 

  76. #define TAMP_BOOT_DEVICE_MASK		GENMASK(7, 4)
    77. 

  77. #define TAMP_BOOT_INSTANCE_MASK		GENMASK(3, 0)
    78. 

  78. 

  79. #endif /* __ASSEMBLY__*/
    80. 

  80. #endif /* _MACH_STM32_H_ */
    81.