omap4.h 4.5 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Authors:
  6. * Aneesh V <aneesh@ti.com>
  7. *
  8. * Derived from OMAP3 work by
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <x0khasim@ti.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef _OMAP4_H_
  31. #define _OMAP4_H_
  32. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  33. #include <asm/types.h>
  34. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  35. /*
  36. * L4 Peripherals - L4 Wakeup and L4 Core now
  37. */
  38. #define OMAP44XX_L4_CORE_BASE 0x4A000000
  39. #define OMAP44XX_L4_WKUP_BASE 0x4A300000
  40. #define OMAP44XX_L4_PER_BASE 0x48000000
  41. #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
  42. #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
  43. /* CONTROL */
  44. #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
  45. #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
  46. #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
  47. /* LPDDR2 IO regs */
  48. #define LPDDR2_IO_REGS_BASE 0x4A100638
  49. #define CONTROL_EFUSE_2 0x4A100704
  50. /* CONTROL_ID_CODE */
  51. #define CONTROL_ID_CODE 0x4A002204
  52. #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
  53. #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
  54. #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
  55. #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
  56. #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
  57. /* UART */
  58. #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
  59. #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
  60. #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
  61. /* General Purpose Timers */
  62. #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
  63. #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
  64. #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
  65. /* Watchdog Timer2 - MPU watchdog */
  66. #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
  67. /* 32KTIMER */
  68. #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
  69. /* GPMC */
  70. #define OMAP44XX_GPMC_BASE 0x50000000
  71. /*
  72. * Hardware Register Details
  73. */
  74. /* Watchdog Timer */
  75. #define WD_UNLOCK1 0xAAAA
  76. #define WD_UNLOCK2 0x5555
  77. /* GP Timer */
  78. #define TCLR_ST (0x1 << 0)
  79. #define TCLR_AR (0x1 << 1)
  80. #define TCLR_PRE (0x1 << 5)
  81. /*
  82. * PRCM
  83. */
  84. /* PRM */
  85. #define PRM_BASE 0x4A306000
  86. #define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
  87. #define PRM_RSTCTRL PRM_DEVICE_BASE
  88. #define PRM_RSTCTRL_RESET 0x01
  89. #ifndef __ASSEMBLY__
  90. struct s32ktimer {
  91. unsigned char res[0x10];
  92. unsigned int s32k_cr; /* 0x10 */
  93. };
  94. #endif /* __ASSEMBLY__ */
  95. /*
  96. * Non-secure SRAM Addresses
  97. * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  98. * at 0x40304000(EMU base) so that our code works for both EMU and GP
  99. */
  100. #define NON_SECURE_SRAM_START 0x40304000
  101. #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
  102. /* base address for indirect vectors (internal boot mode) */
  103. #define SRAM_ROM_VECT_BASE 0x4030D000
  104. /* Temporary SRAM stack used while low level init is done */
  105. #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
  106. #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
  107. /* SRAM scratch space entries */
  108. #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
  109. #define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
  110. #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
  111. #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
  112. #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
  113. /* Silicon revisions */
  114. #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
  115. #define OMAP4430_ES1_0 0x44300100
  116. #define OMAP4430_ES2_0 0x44300200
  117. #define OMAP4430_ES2_1 0x44300210
  118. #define OMAP4430_ES2_2 0x44300220
  119. #define OMAP4430_ES2_3 0x44300230
  120. #define OMAP4460_ES1_0 0x44600100
  121. /* ROM code defines */
  122. /* Boot device */
  123. #define BOOT_DEVICE_MASK 0xFF
  124. #define BOOT_DEVICE_OFFSET 0x8
  125. #define DEV_DESC_PTR_OFFSET 0x4
  126. #define DEV_DATA_PTR_OFFSET 0x18
  127. #define BOOT_MODE_OFFSET 0x8
  128. #endif