cache-cp15.c 6.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/system.h>
  9. #include <asm/cache.h>
  10. #include <linux/compiler.h>
  11. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  12. DECLARE_GLOBAL_DATA_PTR;
  13. __weak void arm_init_before_mmu(void)
  14. {
  15. }
  16. __weak void arm_init_domains(void)
  17. {
  18. }
  19. static void cp_delay (void)
  20. {
  21. volatile int i;
  22. /* copro seems to need some delay between reading and writing */
  23. for (i = 0; i < 100; i++)
  24. nop();
  25. asm volatile("" : : : "memory");
  26. }
  27. void set_section_dcache(int section, enum dcache_option option)
  28. {
  29. #ifdef CONFIG_ARMV7_LPAE
  30. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  31. /* Need to set the access flag to not fault */
  32. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  33. #else
  34. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  35. u32 value = TTB_SECT_AP;
  36. #endif
  37. /* Add the page offset */
  38. value |= ((u32)section << MMU_SECTION_SHIFT);
  39. /* Add caching bits */
  40. value |= option;
  41. /* Set PTE */
  42. page_table[section] = value;
  43. }
  44. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  45. {
  46. debug("%s: Warning: not implemented\n", __func__);
  47. }
  48. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  49. enum dcache_option option)
  50. {
  51. #ifdef CONFIG_ARMV7_LPAE
  52. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  53. #else
  54. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  55. #endif
  56. unsigned long startpt, stoppt;
  57. unsigned long upto, end;
  58. end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
  59. start = start >> MMU_SECTION_SHIFT;
  60. #ifdef CONFIG_ARMV7_LPAE
  61. debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
  62. option);
  63. #else
  64. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  65. option);
  66. #endif
  67. for (upto = start; upto < end; upto++)
  68. set_section_dcache(upto, option);
  69. /*
  70. * Make sure range is cache line aligned
  71. * Only CPU maintains page tables, hence it is safe to always
  72. * flush complete cache lines...
  73. */
  74. startpt = (unsigned long)&page_table[start];
  75. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  76. stoppt = (unsigned long)&page_table[end];
  77. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  78. mmu_page_table_flush(startpt, stoppt);
  79. }
  80. __weak void dram_bank_mmu_setup(int bank)
  81. {
  82. bd_t *bd = gd->bd;
  83. int i;
  84. debug("%s: bank: %d\n", __func__, bank);
  85. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  86. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  87. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  88. i++) {
  89. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  90. set_section_dcache(i, DCACHE_WRITETHROUGH);
  91. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  92. set_section_dcache(i, DCACHE_WRITEALLOC);
  93. #else
  94. set_section_dcache(i, DCACHE_WRITEBACK);
  95. #endif
  96. }
  97. }
  98. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  99. static inline void mmu_setup(void)
  100. {
  101. int i;
  102. u32 reg;
  103. arm_init_before_mmu();
  104. /* Set up an identity-mapping for all 4GB, rw for everyone */
  105. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  106. set_section_dcache(i, DCACHE_OFF);
  107. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  108. dram_bank_mmu_setup(i);
  109. }
  110. #ifdef CONFIG_ARMV7_LPAE
  111. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  112. for (i = 0; i < 4; i++) {
  113. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  114. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  115. page_table[i] = tpt | TTB_PAGETABLE;
  116. }
  117. reg = TTBCR_EAE;
  118. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  119. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  120. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  121. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  122. #else
  123. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  124. #endif
  125. if (is_hyp()) {
  126. /* Set HCTR to enable LPAE */
  127. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  128. : : "r" (reg) : "memory");
  129. /* Set HTTBR0 */
  130. asm volatile("mcrr p15, 4, %0, %1, c2"
  131. :
  132. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  133. : "memory");
  134. /* Set HMAIR */
  135. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  136. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  137. } else {
  138. /* Set TTBCR to enable LPAE */
  139. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  140. : : "r" (reg) : "memory");
  141. /* Set 64-bit TTBR0 */
  142. asm volatile("mcrr p15, 0, %0, %1, c2"
  143. :
  144. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  145. : "memory");
  146. /* Set MAIR */
  147. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  148. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  149. }
  150. #elif defined(CONFIG_CPU_V7)
  151. /* Set TTBR0 */
  152. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  153. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  154. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  155. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  156. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  157. #else
  158. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  159. #endif
  160. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  161. : : "r" (reg) : "memory");
  162. #else
  163. /* Copy the page table address to cp15 */
  164. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  165. : : "r" (gd->arch.tlb_addr) : "memory");
  166. #endif
  167. /* Set the access control to all-supervisor */
  168. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  169. : : "r" (~0));
  170. arm_init_domains();
  171. /* and enable the mmu */
  172. reg = get_cr(); /* get control reg. */
  173. cp_delay();
  174. set_cr(reg | CR_M);
  175. }
  176. static int mmu_enabled(void)
  177. {
  178. return get_cr() & CR_M;
  179. }
  180. /* cache_bit must be either CR_I or CR_C */
  181. static void cache_enable(uint32_t cache_bit)
  182. {
  183. uint32_t reg;
  184. /* The data cache is not active unless the mmu is enabled too */
  185. if ((cache_bit == CR_C) && !mmu_enabled())
  186. mmu_setup();
  187. reg = get_cr(); /* get control reg. */
  188. cp_delay();
  189. set_cr(reg | cache_bit);
  190. }
  191. /* cache_bit must be either CR_I or CR_C */
  192. static void cache_disable(uint32_t cache_bit)
  193. {
  194. uint32_t reg;
  195. reg = get_cr();
  196. cp_delay();
  197. if (cache_bit == CR_C) {
  198. /* if cache isn;t enabled no need to disable */
  199. if ((reg & CR_C) != CR_C)
  200. return;
  201. /* if disabling data cache, disable mmu too */
  202. cache_bit |= CR_M;
  203. }
  204. reg = get_cr();
  205. cp_delay();
  206. if (cache_bit == (CR_C | CR_M))
  207. flush_dcache_all();
  208. set_cr(reg & ~cache_bit);
  209. }
  210. #endif
  211. #ifdef CONFIG_SYS_ICACHE_OFF
  212. void icache_enable (void)
  213. {
  214. return;
  215. }
  216. void icache_disable (void)
  217. {
  218. return;
  219. }
  220. int icache_status (void)
  221. {
  222. return 0; /* always off */
  223. }
  224. #else
  225. void icache_enable(void)
  226. {
  227. cache_enable(CR_I);
  228. }
  229. void icache_disable(void)
  230. {
  231. cache_disable(CR_I);
  232. }
  233. int icache_status(void)
  234. {
  235. return (get_cr() & CR_I) != 0;
  236. }
  237. #endif
  238. #ifdef CONFIG_SYS_DCACHE_OFF
  239. void dcache_enable (void)
  240. {
  241. return;
  242. }
  243. void dcache_disable (void)
  244. {
  245. return;
  246. }
  247. int dcache_status (void)
  248. {
  249. return 0; /* always off */
  250. }
  251. #else
  252. void dcache_enable(void)
  253. {
  254. cache_enable(CR_C);
  255. }
  256. void dcache_disable(void)
  257. {
  258. cache_disable(CR_C);
  259. }
  260. int dcache_status(void)
  261. {
  262. return (get_cr() & CR_C) != 0;
  263. }
  264. #endif