system.h 12 KB

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  1. #ifndef __ASM_ARM_SYSTEM_H
  2. #define __ASM_ARM_SYSTEM_H
  3. #include <common.h>
  4. #include <linux/compiler.h>
  5. #include <asm/barriers.h>
  6. #ifdef CONFIG_ARM64
  7. /*
  8. * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
  9. */
  10. #define CR_M (1 << 0) /* MMU enable */
  11. #define CR_A (1 << 1) /* Alignment abort enable */
  12. #define CR_C (1 << 2) /* Dcache enable */
  13. #define CR_SA (1 << 3) /* Stack Alignment Check Enable */
  14. #define CR_I (1 << 12) /* Icache enable */
  15. #define CR_WXN (1 << 19) /* Write Permision Imply XN */
  16. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  17. #ifndef __ASSEMBLY__
  18. u64 get_page_table_size(void);
  19. #define PGTABLE_SIZE get_page_table_size()
  20. /* 2MB granularity */
  21. #define MMU_SECTION_SHIFT 21
  22. #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
  23. /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
  24. enum dcache_option {
  25. DCACHE_OFF = 0 << 2,
  26. DCACHE_WRITETHROUGH = 3 << 2,
  27. DCACHE_WRITEBACK = 4 << 2,
  28. DCACHE_WRITEALLOC = 4 << 2,
  29. };
  30. #define wfi() \
  31. ({asm volatile( \
  32. "wfi" : : : "memory"); \
  33. })
  34. static inline unsigned int current_el(void)
  35. {
  36. unsigned int el;
  37. asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
  38. return el >> 2;
  39. }
  40. static inline unsigned int get_sctlr(void)
  41. {
  42. unsigned int el, val;
  43. el = current_el();
  44. if (el == 1)
  45. asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
  46. else if (el == 2)
  47. asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
  48. else
  49. asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
  50. return val;
  51. }
  52. static inline void set_sctlr(unsigned int val)
  53. {
  54. unsigned int el;
  55. el = current_el();
  56. if (el == 1)
  57. asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
  58. else if (el == 2)
  59. asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
  60. else
  61. asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
  62. asm volatile("isb");
  63. }
  64. static inline unsigned long read_mpidr(void)
  65. {
  66. unsigned long val;
  67. asm volatile("mrs %0, mpidr_el1" : "=r" (val));
  68. return val;
  69. }
  70. #define BSP_COREID 0
  71. void __asm_flush_dcache_all(void);
  72. void __asm_invalidate_dcache_all(void);
  73. void __asm_flush_dcache_range(u64 start, u64 end);
  74. void __asm_invalidate_tlb_all(void);
  75. void __asm_invalidate_icache_all(void);
  76. int __asm_invalidate_l3_dcache(void);
  77. int __asm_flush_l3_dcache(void);
  78. int __asm_invalidate_l3_icache(void);
  79. void __asm_switch_ttbr(u64 new_ttbr);
  80. void armv8_switch_to_el2(void);
  81. void armv8_switch_to_el1(void);
  82. void gic_init(void);
  83. void gic_send_sgi(unsigned long sgino);
  84. void wait_for_wakeup(void);
  85. void protect_secure_region(void);
  86. void smp_kick_all_cpus(void);
  87. void flush_l3_cache(void);
  88. /*
  89. *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
  90. * DEN0028A
  91. *
  92. * @args: input and output arguments
  93. *
  94. */
  95. void smc_call(struct pt_regs *args);
  96. void __noreturn psci_system_reset(void);
  97. void __noreturn psci_system_off(void);
  98. #endif /* __ASSEMBLY__ */
  99. #else /* CONFIG_ARM64 */
  100. #ifdef __KERNEL__
  101. #define CPU_ARCH_UNKNOWN 0
  102. #define CPU_ARCH_ARMv3 1
  103. #define CPU_ARCH_ARMv4 2
  104. #define CPU_ARCH_ARMv4T 3
  105. #define CPU_ARCH_ARMv5 4
  106. #define CPU_ARCH_ARMv5T 5
  107. #define CPU_ARCH_ARMv5TE 6
  108. #define CPU_ARCH_ARMv5TEJ 7
  109. #define CPU_ARCH_ARMv6 8
  110. #define CPU_ARCH_ARMv7 9
  111. /*
  112. * CR1 bits (CP#15 CR1)
  113. */
  114. #define CR_M (1 << 0) /* MMU enable */
  115. #define CR_A (1 << 1) /* Alignment abort enable */
  116. #define CR_C (1 << 2) /* Dcache enable */
  117. #define CR_W (1 << 3) /* Write buffer enable */
  118. #define CR_P (1 << 4) /* 32-bit exception handler */
  119. #define CR_D (1 << 5) /* 32-bit data address range */
  120. #define CR_L (1 << 6) /* Implementation defined */
  121. #define CR_B (1 << 7) /* Big endian */
  122. #define CR_S (1 << 8) /* System MMU protection */
  123. #define CR_R (1 << 9) /* ROM MMU protection */
  124. #define CR_F (1 << 10) /* Implementation defined */
  125. #define CR_Z (1 << 11) /* Implementation defined */
  126. #define CR_I (1 << 12) /* Icache enable */
  127. #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
  128. #define CR_RR (1 << 14) /* Round Robin cache replacement */
  129. #define CR_L4 (1 << 15) /* LDR pc can set T bit */
  130. #define CR_DT (1 << 16)
  131. #define CR_IT (1 << 18)
  132. #define CR_ST (1 << 19)
  133. #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
  134. #define CR_U (1 << 22) /* Unaligned access operation */
  135. #define CR_XP (1 << 23) /* Extended page tables */
  136. #define CR_VE (1 << 24) /* Vectored interrupts */
  137. #define CR_EE (1 << 25) /* Exception (Big) Endian */
  138. #define CR_TRE (1 << 28) /* TEX remap enable */
  139. #define CR_AFE (1 << 29) /* Access flag enable */
  140. #define CR_TE (1 << 30) /* Thumb exception enable */
  141. #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
  142. #define PGTABLE_SIZE (4096 * 5)
  143. #elif !defined(PGTABLE_SIZE)
  144. #define PGTABLE_SIZE (4096 * 4)
  145. #endif
  146. /*
  147. * This is used to ensure the compiler did actually allocate the register we
  148. * asked it for some inline assembly sequences. Apparently we can't trust
  149. * the compiler from one version to another so a bit of paranoia won't hurt.
  150. * This string is meant to be concatenated with the inline asm string and
  151. * will cause compilation to stop on mismatch.
  152. * (for details, see gcc PR 15089)
  153. */
  154. #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
  155. #ifndef __ASSEMBLY__
  156. /**
  157. * save_boot_params() - Save boot parameters before starting reset sequence
  158. *
  159. * If you provide this function it will be called immediately U-Boot starts,
  160. * both for SPL and U-Boot proper.
  161. *
  162. * All registers are unchanged from U-Boot entry. No registers need be
  163. * preserved.
  164. *
  165. * This is not a normal C function. There is no stack. Return by branching to
  166. * save_boot_params_ret.
  167. *
  168. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
  169. */
  170. /**
  171. * save_boot_params_ret() - Return from save_boot_params()
  172. *
  173. * If you provide save_boot_params(), then you should jump back to this
  174. * function when done. Try to preserve all registers.
  175. *
  176. * If your implementation of save_boot_params() is in C then it is acceptable
  177. * to simply call save_boot_params_ret() at the end of your function. Since
  178. * there is no link register set up, you cannot just exit the function. U-Boot
  179. * will return to the (initialised) value of lr, and likely crash/hang.
  180. *
  181. * If your implementation of save_boot_params() is in assembler then you
  182. * should use 'b' or 'bx' to return to save_boot_params_ret.
  183. */
  184. void save_boot_params_ret(void);
  185. #ifdef CONFIG_ARMV7_LPAE
  186. void switch_to_hypervisor_ret(void);
  187. #endif
  188. #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  189. #ifdef __ARM_ARCH_7A__
  190. #define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
  191. #else
  192. #define wfi()
  193. #endif
  194. static inline unsigned long get_cpsr(void)
  195. {
  196. unsigned long cpsr;
  197. asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
  198. return cpsr;
  199. }
  200. static inline int is_hyp(void)
  201. {
  202. #ifdef CONFIG_ARMV7_LPAE
  203. /* HYP mode requires LPAE ... */
  204. return ((get_cpsr() & 0x1f) == 0x1a);
  205. #else
  206. /* ... so without LPAE support we can optimize all hyp code away */
  207. return 0;
  208. #endif
  209. }
  210. static inline unsigned int get_cr(void)
  211. {
  212. unsigned int val;
  213. if (is_hyp())
  214. asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
  215. :
  216. : "cc");
  217. else
  218. asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
  219. :
  220. : "cc");
  221. return val;
  222. }
  223. static inline void set_cr(unsigned int val)
  224. {
  225. if (is_hyp())
  226. asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
  227. : "r" (val)
  228. : "cc");
  229. else
  230. asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
  231. : "r" (val)
  232. : "cc");
  233. isb();
  234. }
  235. static inline unsigned int get_dacr(void)
  236. {
  237. unsigned int val;
  238. asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
  239. return val;
  240. }
  241. static inline void set_dacr(unsigned int val)
  242. {
  243. asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
  244. : : "r" (val) : "cc");
  245. isb();
  246. }
  247. #ifdef CONFIG_ARMV7_LPAE
  248. /* Long-Descriptor Translation Table Level 1/2 Bits */
  249. #define TTB_SECT_XN_MASK (1ULL << 54)
  250. #define TTB_SECT_NG_MASK (1 << 11)
  251. #define TTB_SECT_AF (1 << 10)
  252. #define TTB_SECT_SH_MASK (3 << 8)
  253. #define TTB_SECT_NS_MASK (1 << 5)
  254. #define TTB_SECT_AP (1 << 6)
  255. /* Note: TTB AP bits are set elsewhere */
  256. #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
  257. #define TTB_SECT (1 << 0)
  258. #define TTB_PAGETABLE (3 << 0)
  259. /* TTBCR flags */
  260. #define TTBCR_EAE (1 << 31)
  261. #define TTBCR_T0SZ(x) ((x) << 0)
  262. #define TTBCR_T1SZ(x) ((x) << 16)
  263. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  264. #define TTBCR_IRGN0_NC (0 << 8)
  265. #define TTBCR_IRGN0_WBWA (1 << 8)
  266. #define TTBCR_IRGN0_WT (2 << 8)
  267. #define TTBCR_IRGN0_WBNWA (3 << 8)
  268. #define TTBCR_IRGN0_MASK (3 << 8)
  269. #define TTBCR_ORGN0_NC (0 << 10)
  270. #define TTBCR_ORGN0_WBWA (1 << 10)
  271. #define TTBCR_ORGN0_WT (2 << 10)
  272. #define TTBCR_ORGN0_WBNWA (3 << 10)
  273. #define TTBCR_ORGN0_MASK (3 << 10)
  274. #define TTBCR_SHARED_NON (0 << 12)
  275. #define TTBCR_SHARED_OUTER (2 << 12)
  276. #define TTBCR_SHARED_INNER (3 << 12)
  277. #define TTBCR_EPD0 (0 << 7)
  278. /*
  279. * Memory types
  280. */
  281. #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
  282. (0xcc << (2 * 8)) | (0xff << (3 * 8)))
  283. /* options available for data cache on each page */
  284. enum dcache_option {
  285. DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
  286. DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
  287. DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
  288. DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
  289. };
  290. #elif defined(CONFIG_CPU_V7)
  291. /* Short-Descriptor Translation Table Level 1 Bits */
  292. #define TTB_SECT_NS_MASK (1 << 19)
  293. #define TTB_SECT_NG_MASK (1 << 17)
  294. #define TTB_SECT_S_MASK (1 << 16)
  295. /* Note: TTB AP bits are set elsewhere */
  296. #define TTB_SECT_AP (3 << 10)
  297. #define TTB_SECT_TEX(x) ((x & 0x7) << 12)
  298. #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
  299. #define TTB_SECT_XN_MASK (1 << 4)
  300. #define TTB_SECT_C_MASK (1 << 3)
  301. #define TTB_SECT_B_MASK (1 << 2)
  302. #define TTB_SECT (2 << 0)
  303. /* options available for data cache on each page */
  304. enum dcache_option {
  305. DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
  306. DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
  307. DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
  308. DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
  309. };
  310. #else
  311. #define TTB_SECT_AP (3 << 10)
  312. /* options available for data cache on each page */
  313. enum dcache_option {
  314. DCACHE_OFF = 0x12,
  315. DCACHE_WRITETHROUGH = 0x1a,
  316. DCACHE_WRITEBACK = 0x1e,
  317. DCACHE_WRITEALLOC = 0x16,
  318. };
  319. #endif
  320. /* Size of an MMU section */
  321. enum {
  322. #ifdef CONFIG_ARMV7_LPAE
  323. MMU_SECTION_SHIFT = 21, /* 2MB */
  324. #else
  325. MMU_SECTION_SHIFT = 20, /* 1MB */
  326. #endif
  327. MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
  328. };
  329. #ifdef CONFIG_CPU_V7
  330. /* TTBR0 bits */
  331. #define TTBR0_BASE_ADDR_MASK 0xFFFFC000
  332. #define TTBR0_RGN_NC (0 << 3)
  333. #define TTBR0_RGN_WBWA (1 << 3)
  334. #define TTBR0_RGN_WT (2 << 3)
  335. #define TTBR0_RGN_WB (3 << 3)
  336. /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
  337. #define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
  338. #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
  339. #define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
  340. #define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
  341. #endif
  342. /**
  343. * Register an update to the page tables, and flush the TLB
  344. *
  345. * \param start start address of update in page table
  346. * \param stop stop address of update in page table
  347. */
  348. void mmu_page_table_flush(unsigned long start, unsigned long stop);
  349. #endif /* __ASSEMBLY__ */
  350. #define arch_align_stack(x) (x)
  351. #endif /* __KERNEL__ */
  352. #endif /* CONFIG_ARM64 */
  353. #ifndef __ASSEMBLY__
  354. /**
  355. * Change the cache settings for a region.
  356. *
  357. * \param start start address of memory region to change
  358. * \param size size of memory region to change
  359. * \param option dcache option to select
  360. */
  361. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  362. enum dcache_option option);
  363. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  364. void noncached_init(void);
  365. phys_addr_t noncached_alloc(size_t size, size_t align);
  366. #endif /* CONFIG_SYS_NONCACHED_MEMORY */
  367. #endif /* __ASSEMBLY__ */
  368. #endif