phy.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Generic PHY Management code
  4. *
  5. * Copyright 2011 Freescale Semiconductor, Inc.
  6. * author Andy Fleming
  7. *
  8. * Based loosely off of Linux's PHY Lib
  9. */
  10. #include <common.h>
  11. #include <console.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <net.h>
  15. #include <command.h>
  16. #include <miiphy.h>
  17. #include <phy.h>
  18. #include <errno.h>
  19. #include <linux/err.h>
  20. #include <linux/compiler.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* Generic PHY support and helper functions */
  23. /**
  24. * genphy_config_advert - sanitize and advertise auto-negotiation parameters
  25. * @phydev: target phy_device struct
  26. *
  27. * Description: Writes MII_ADVERTISE with the appropriate values,
  28. * after sanitizing the values to make sure we only advertise
  29. * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
  30. * hasn't changed, and > 0 if it has changed.
  31. */
  32. static int genphy_config_advert(struct phy_device *phydev)
  33. {
  34. u32 advertise;
  35. int oldadv, adv, bmsr;
  36. int err, changed = 0;
  37. /* Only allow advertising what this PHY supports */
  38. phydev->advertising &= phydev->supported;
  39. advertise = phydev->advertising;
  40. /* Setup standard advertisement */
  41. adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
  42. oldadv = adv;
  43. if (adv < 0)
  44. return adv;
  45. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
  46. ADVERTISE_PAUSE_ASYM);
  47. if (advertise & ADVERTISED_10baseT_Half)
  48. adv |= ADVERTISE_10HALF;
  49. if (advertise & ADVERTISED_10baseT_Full)
  50. adv |= ADVERTISE_10FULL;
  51. if (advertise & ADVERTISED_100baseT_Half)
  52. adv |= ADVERTISE_100HALF;
  53. if (advertise & ADVERTISED_100baseT_Full)
  54. adv |= ADVERTISE_100FULL;
  55. if (advertise & ADVERTISED_Pause)
  56. adv |= ADVERTISE_PAUSE_CAP;
  57. if (advertise & ADVERTISED_Asym_Pause)
  58. adv |= ADVERTISE_PAUSE_ASYM;
  59. if (advertise & ADVERTISED_1000baseX_Half)
  60. adv |= ADVERTISE_1000XHALF;
  61. if (advertise & ADVERTISED_1000baseX_Full)
  62. adv |= ADVERTISE_1000XFULL;
  63. if (adv != oldadv) {
  64. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
  65. if (err < 0)
  66. return err;
  67. changed = 1;
  68. }
  69. bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  70. if (bmsr < 0)
  71. return bmsr;
  72. /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
  73. * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
  74. * logical 1.
  75. */
  76. if (!(bmsr & BMSR_ESTATEN))
  77. return changed;
  78. /* Configure gigabit if it's supported */
  79. adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
  80. oldadv = adv;
  81. if (adv < 0)
  82. return adv;
  83. adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  84. if (phydev->supported & (SUPPORTED_1000baseT_Half |
  85. SUPPORTED_1000baseT_Full)) {
  86. if (advertise & SUPPORTED_1000baseT_Half)
  87. adv |= ADVERTISE_1000HALF;
  88. if (advertise & SUPPORTED_1000baseT_Full)
  89. adv |= ADVERTISE_1000FULL;
  90. }
  91. if (adv != oldadv)
  92. changed = 1;
  93. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv);
  94. if (err < 0)
  95. return err;
  96. return changed;
  97. }
  98. /**
  99. * genphy_setup_forced - configures/forces speed/duplex from @phydev
  100. * @phydev: target phy_device struct
  101. *
  102. * Description: Configures MII_BMCR to force speed/duplex
  103. * to the values in phydev. Assumes that the values are valid.
  104. */
  105. static int genphy_setup_forced(struct phy_device *phydev)
  106. {
  107. int err;
  108. int ctl = BMCR_ANRESTART;
  109. phydev->pause = 0;
  110. phydev->asym_pause = 0;
  111. if (phydev->speed == SPEED_1000)
  112. ctl |= BMCR_SPEED1000;
  113. else if (phydev->speed == SPEED_100)
  114. ctl |= BMCR_SPEED100;
  115. if (phydev->duplex == DUPLEX_FULL)
  116. ctl |= BMCR_FULLDPLX;
  117. err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
  118. return err;
  119. }
  120. /**
  121. * genphy_restart_aneg - Enable and Restart Autonegotiation
  122. * @phydev: target phy_device struct
  123. */
  124. int genphy_restart_aneg(struct phy_device *phydev)
  125. {
  126. int ctl;
  127. ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  128. if (ctl < 0)
  129. return ctl;
  130. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  131. /* Don't isolate the PHY if we're negotiating */
  132. ctl &= ~(BMCR_ISOLATE);
  133. ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
  134. return ctl;
  135. }
  136. /**
  137. * genphy_config_aneg - restart auto-negotiation or write BMCR
  138. * @phydev: target phy_device struct
  139. *
  140. * Description: If auto-negotiation is enabled, we configure the
  141. * advertising, and then restart auto-negotiation. If it is not
  142. * enabled, then we write the BMCR.
  143. */
  144. int genphy_config_aneg(struct phy_device *phydev)
  145. {
  146. int result;
  147. if (phydev->autoneg != AUTONEG_ENABLE)
  148. return genphy_setup_forced(phydev);
  149. result = genphy_config_advert(phydev);
  150. if (result < 0) /* error */
  151. return result;
  152. if (result == 0) {
  153. /*
  154. * Advertisment hasn't changed, but maybe aneg was never on to
  155. * begin with? Or maybe phy was isolated?
  156. */
  157. int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  158. if (ctl < 0)
  159. return ctl;
  160. if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
  161. result = 1; /* do restart aneg */
  162. }
  163. /*
  164. * Only restart aneg if we are advertising something different
  165. * than we were before.
  166. */
  167. if (result > 0)
  168. result = genphy_restart_aneg(phydev);
  169. return result;
  170. }
  171. /**
  172. * genphy_update_link - update link status in @phydev
  173. * @phydev: target phy_device struct
  174. *
  175. * Description: Update the value in phydev->link to reflect the
  176. * current link value. In order to do this, we need to read
  177. * the status register twice, keeping the second value.
  178. */
  179. int genphy_update_link(struct phy_device *phydev)
  180. {
  181. unsigned int mii_reg;
  182. /*
  183. * Wait if the link is up, and autonegotiation is in progress
  184. * (ie - we're capable and it's not done)
  185. */
  186. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  187. /*
  188. * If we already saw the link up, and it hasn't gone down, then
  189. * we don't need to wait for autoneg again
  190. */
  191. if (phydev->link && mii_reg & BMSR_LSTATUS)
  192. return 0;
  193. if ((phydev->autoneg == AUTONEG_ENABLE) &&
  194. !(mii_reg & BMSR_ANEGCOMPLETE)) {
  195. int i = 0;
  196. printf("%s Waiting for PHY auto negotiation to complete",
  197. phydev->dev->name);
  198. while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
  199. /*
  200. * Timeout reached ?
  201. */
  202. if (i > PHY_ANEG_TIMEOUT) {
  203. printf(" TIMEOUT !\n");
  204. phydev->link = 0;
  205. return -ETIMEDOUT;
  206. }
  207. if (ctrlc()) {
  208. puts("user interrupt!\n");
  209. phydev->link = 0;
  210. return -EINTR;
  211. }
  212. if ((i++ % 500) == 0)
  213. printf(".");
  214. udelay(1000); /* 1 ms */
  215. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  216. }
  217. printf(" done\n");
  218. phydev->link = 1;
  219. } else {
  220. /* Read the link a second time to clear the latched state */
  221. mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  222. if (mii_reg & BMSR_LSTATUS)
  223. phydev->link = 1;
  224. else
  225. phydev->link = 0;
  226. }
  227. return 0;
  228. }
  229. /*
  230. * Generic function which updates the speed and duplex. If
  231. * autonegotiation is enabled, it uses the AND of the link
  232. * partner's advertised capabilities and our advertised
  233. * capabilities. If autonegotiation is disabled, we use the
  234. * appropriate bits in the control register.
  235. *
  236. * Stolen from Linux's mii.c and phy_device.c
  237. */
  238. int genphy_parse_link(struct phy_device *phydev)
  239. {
  240. int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  241. /* We're using autonegotiation */
  242. if (phydev->autoneg == AUTONEG_ENABLE) {
  243. u32 lpa = 0;
  244. int gblpa = 0;
  245. u32 estatus = 0;
  246. /* Check for gigabit capability */
  247. if (phydev->supported & (SUPPORTED_1000baseT_Full |
  248. SUPPORTED_1000baseT_Half)) {
  249. /* We want a list of states supported by
  250. * both PHYs in the link
  251. */
  252. gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
  253. if (gblpa < 0) {
  254. debug("Could not read MII_STAT1000. ");
  255. debug("Ignoring gigabit capability\n");
  256. gblpa = 0;
  257. }
  258. gblpa &= phy_read(phydev,
  259. MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
  260. }
  261. /* Set the baseline so we only have to set them
  262. * if they're different
  263. */
  264. phydev->speed = SPEED_10;
  265. phydev->duplex = DUPLEX_HALF;
  266. /* Check the gigabit fields */
  267. if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
  268. phydev->speed = SPEED_1000;
  269. if (gblpa & PHY_1000BTSR_1000FD)
  270. phydev->duplex = DUPLEX_FULL;
  271. /* We're done! */
  272. return 0;
  273. }
  274. lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
  275. lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
  276. if (lpa & (LPA_100FULL | LPA_100HALF)) {
  277. phydev->speed = SPEED_100;
  278. if (lpa & LPA_100FULL)
  279. phydev->duplex = DUPLEX_FULL;
  280. } else if (lpa & LPA_10FULL) {
  281. phydev->duplex = DUPLEX_FULL;
  282. }
  283. /*
  284. * Extended status may indicate that the PHY supports
  285. * 1000BASE-T/X even though the 1000BASE-T registers
  286. * are missing. In this case we can't tell whether the
  287. * peer also supports it, so we only check extended
  288. * status if the 1000BASE-T registers are actually
  289. * missing.
  290. */
  291. if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP))
  292. estatus = phy_read(phydev, MDIO_DEVAD_NONE,
  293. MII_ESTATUS);
  294. if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF |
  295. ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
  296. phydev->speed = SPEED_1000;
  297. if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL))
  298. phydev->duplex = DUPLEX_FULL;
  299. }
  300. } else {
  301. u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
  302. phydev->speed = SPEED_10;
  303. phydev->duplex = DUPLEX_HALF;
  304. if (bmcr & BMCR_FULLDPLX)
  305. phydev->duplex = DUPLEX_FULL;
  306. if (bmcr & BMCR_SPEED1000)
  307. phydev->speed = SPEED_1000;
  308. else if (bmcr & BMCR_SPEED100)
  309. phydev->speed = SPEED_100;
  310. }
  311. return 0;
  312. }
  313. int genphy_config(struct phy_device *phydev)
  314. {
  315. int val;
  316. u32 features;
  317. features = (SUPPORTED_TP | SUPPORTED_MII
  318. | SUPPORTED_AUI | SUPPORTED_FIBRE |
  319. SUPPORTED_BNC);
  320. /* Do we support autonegotiation? */
  321. val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
  322. if (val < 0)
  323. return val;
  324. if (val & BMSR_ANEGCAPABLE)
  325. features |= SUPPORTED_Autoneg;
  326. if (val & BMSR_100FULL)
  327. features |= SUPPORTED_100baseT_Full;
  328. if (val & BMSR_100HALF)
  329. features |= SUPPORTED_100baseT_Half;
  330. if (val & BMSR_10FULL)
  331. features |= SUPPORTED_10baseT_Full;
  332. if (val & BMSR_10HALF)
  333. features |= SUPPORTED_10baseT_Half;
  334. if (val & BMSR_ESTATEN) {
  335. val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
  336. if (val < 0)
  337. return val;
  338. if (val & ESTATUS_1000_TFULL)
  339. features |= SUPPORTED_1000baseT_Full;
  340. if (val & ESTATUS_1000_THALF)
  341. features |= SUPPORTED_1000baseT_Half;
  342. if (val & ESTATUS_1000_XFULL)
  343. features |= SUPPORTED_1000baseX_Full;
  344. if (val & ESTATUS_1000_XHALF)
  345. features |= SUPPORTED_1000baseX_Half;
  346. }
  347. phydev->supported &= features;
  348. phydev->advertising &= features;
  349. genphy_config_aneg(phydev);
  350. return 0;
  351. }
  352. int genphy_startup(struct phy_device *phydev)
  353. {
  354. int ret;
  355. ret = genphy_update_link(phydev);
  356. if (ret)
  357. return ret;
  358. return genphy_parse_link(phydev);
  359. }
  360. int genphy_shutdown(struct phy_device *phydev)
  361. {
  362. return 0;
  363. }
  364. static struct phy_driver genphy_driver = {
  365. .uid = 0xffffffff,
  366. .mask = 0xffffffff,
  367. .name = "Generic PHY",
  368. .features = PHY_GBIT_FEATURES | SUPPORTED_MII |
  369. SUPPORTED_AUI | SUPPORTED_FIBRE |
  370. SUPPORTED_BNC,
  371. .config = genphy_config,
  372. .startup = genphy_startup,
  373. .shutdown = genphy_shutdown,
  374. };
  375. static LIST_HEAD(phy_drivers);
  376. int phy_init(void)
  377. {
  378. #ifdef CONFIG_B53_SWITCH
  379. phy_b53_init();
  380. #endif
  381. #ifdef CONFIG_MV88E61XX_SWITCH
  382. phy_mv88e61xx_init();
  383. #endif
  384. #ifdef CONFIG_PHY_AQUANTIA
  385. phy_aquantia_init();
  386. #endif
  387. #ifdef CONFIG_PHY_ATHEROS
  388. phy_atheros_init();
  389. #endif
  390. #ifdef CONFIG_PHY_BROADCOM
  391. phy_broadcom_init();
  392. #endif
  393. #ifdef CONFIG_PHY_CORTINA
  394. phy_cortina_init();
  395. #endif
  396. #ifdef CONFIG_PHY_DAVICOM
  397. phy_davicom_init();
  398. #endif
  399. #ifdef CONFIG_PHY_ET1011C
  400. phy_et1011c_init();
  401. #endif
  402. #ifdef CONFIG_PHY_LXT
  403. phy_lxt_init();
  404. #endif
  405. #ifdef CONFIG_PHY_MARVELL
  406. phy_marvell_init();
  407. #endif
  408. #ifdef CONFIG_PHY_MICREL_KSZ8XXX
  409. phy_micrel_ksz8xxx_init();
  410. #endif
  411. #ifdef CONFIG_PHY_MICREL_KSZ90X1
  412. phy_micrel_ksz90x1_init();
  413. #endif
  414. #ifdef CONFIG_PHY_MESON_GXL
  415. phy_meson_gxl_init();
  416. #endif
  417. #ifdef CONFIG_PHY_NATSEMI
  418. phy_natsemi_init();
  419. #endif
  420. #ifdef CONFIG_PHY_REALTEK
  421. phy_realtek_init();
  422. #endif
  423. #ifdef CONFIG_PHY_SMSC
  424. phy_smsc_init();
  425. #endif
  426. #ifdef CONFIG_PHY_TERANETICS
  427. phy_teranetics_init();
  428. #endif
  429. #ifdef CONFIG_PHY_TI
  430. phy_ti_init();
  431. #endif
  432. #ifdef CONFIG_PHY_VITESSE
  433. phy_vitesse_init();
  434. #endif
  435. #ifdef CONFIG_PHY_XILINX
  436. phy_xilinx_init();
  437. #endif
  438. #ifdef CONFIG_PHY_MSCC
  439. phy_mscc_init();
  440. #endif
  441. #ifdef CONFIG_PHY_FIXED
  442. phy_fixed_init();
  443. #endif
  444. return 0;
  445. }
  446. int phy_register(struct phy_driver *drv)
  447. {
  448. INIT_LIST_HEAD(&drv->list);
  449. list_add_tail(&drv->list, &phy_drivers);
  450. #ifdef CONFIG_NEEDS_MANUAL_RELOC
  451. if (drv->probe)
  452. drv->probe += gd->reloc_off;
  453. if (drv->config)
  454. drv->config += gd->reloc_off;
  455. if (drv->startup)
  456. drv->startup += gd->reloc_off;
  457. if (drv->shutdown)
  458. drv->shutdown += gd->reloc_off;
  459. if (drv->readext)
  460. drv->readext += gd->reloc_off;
  461. if (drv->writeext)
  462. drv->writeext += gd->reloc_off;
  463. #endif
  464. return 0;
  465. }
  466. int phy_set_supported(struct phy_device *phydev, u32 max_speed)
  467. {
  468. /* The default values for phydev->supported are provided by the PHY
  469. * driver "features" member, we want to reset to sane defaults first
  470. * before supporting higher speeds.
  471. */
  472. phydev->supported &= PHY_DEFAULT_FEATURES;
  473. switch (max_speed) {
  474. default:
  475. return -ENOTSUPP;
  476. case SPEED_1000:
  477. phydev->supported |= PHY_1000BT_FEATURES;
  478. /* fall through */
  479. case SPEED_100:
  480. phydev->supported |= PHY_100BT_FEATURES;
  481. /* fall through */
  482. case SPEED_10:
  483. phydev->supported |= PHY_10BT_FEATURES;
  484. }
  485. return 0;
  486. }
  487. static int phy_probe(struct phy_device *phydev)
  488. {
  489. int err = 0;
  490. phydev->advertising = phydev->drv->features;
  491. phydev->supported = phydev->drv->features;
  492. phydev->mmds = phydev->drv->mmds;
  493. if (phydev->drv->probe)
  494. err = phydev->drv->probe(phydev);
  495. return err;
  496. }
  497. static struct phy_driver *generic_for_interface(phy_interface_t interface)
  498. {
  499. #ifdef CONFIG_PHYLIB_10G
  500. if (is_10g_interface(interface))
  501. return &gen10g_driver;
  502. #endif
  503. return &genphy_driver;
  504. }
  505. static struct phy_driver *get_phy_driver(struct phy_device *phydev,
  506. phy_interface_t interface)
  507. {
  508. struct list_head *entry;
  509. int phy_id = phydev->phy_id;
  510. struct phy_driver *drv = NULL;
  511. list_for_each(entry, &phy_drivers) {
  512. drv = list_entry(entry, struct phy_driver, list);
  513. if ((drv->uid & drv->mask) == (phy_id & drv->mask))
  514. return drv;
  515. }
  516. /* If we made it here, there's no driver for this PHY */
  517. return generic_for_interface(interface);
  518. }
  519. static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  520. u32 phy_id,
  521. phy_interface_t interface)
  522. {
  523. struct phy_device *dev;
  524. /*
  525. * We allocate the device, and initialize the
  526. * default values
  527. */
  528. dev = malloc(sizeof(*dev));
  529. if (!dev) {
  530. printf("Failed to allocate PHY device for %s:%d\n",
  531. bus->name, addr);
  532. return NULL;
  533. }
  534. memset(dev, 0, sizeof(*dev));
  535. dev->duplex = -1;
  536. dev->link = 0;
  537. dev->interface = interface;
  538. dev->autoneg = AUTONEG_ENABLE;
  539. dev->addr = addr;
  540. dev->phy_id = phy_id;
  541. dev->bus = bus;
  542. dev->drv = get_phy_driver(dev, interface);
  543. phy_probe(dev);
  544. bus->phymap[addr] = dev;
  545. return dev;
  546. }
  547. /**
  548. * get_phy_id - reads the specified addr for its ID.
  549. * @bus: the target MII bus
  550. * @addr: PHY address on the MII bus
  551. * @phy_id: where to store the ID retrieved.
  552. *
  553. * Description: Reads the ID registers of the PHY at @addr on the
  554. * @bus, stores it in @phy_id and returns zero on success.
  555. */
  556. int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
  557. {
  558. int phy_reg;
  559. /*
  560. * Grab the bits from PHYIR1, and put them
  561. * in the upper half
  562. */
  563. phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  564. if (phy_reg < 0)
  565. return -EIO;
  566. *phy_id = (phy_reg & 0xffff) << 16;
  567. /* Grab the bits from PHYIR2, and put them in the lower half */
  568. phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  569. if (phy_reg < 0)
  570. return -EIO;
  571. *phy_id |= (phy_reg & 0xffff);
  572. return 0;
  573. }
  574. static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
  575. uint phy_mask, int devad,
  576. phy_interface_t interface)
  577. {
  578. u32 phy_id = 0xffffffff;
  579. while (phy_mask) {
  580. int addr = ffs(phy_mask) - 1;
  581. int r = get_phy_id(bus, addr, devad, &phy_id);
  582. /* If the PHY ID is mostly f's, we didn't find anything */
  583. if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff)
  584. return phy_device_create(bus, addr, phy_id, interface);
  585. phy_mask &= ~(1 << addr);
  586. }
  587. return NULL;
  588. }
  589. static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
  590. uint phy_mask,
  591. phy_interface_t interface)
  592. {
  593. /* If we have one, return the existing device, with new interface */
  594. while (phy_mask) {
  595. int addr = ffs(phy_mask) - 1;
  596. if (bus->phymap[addr]) {
  597. bus->phymap[addr]->interface = interface;
  598. return bus->phymap[addr];
  599. }
  600. phy_mask &= ~(1 << addr);
  601. }
  602. return NULL;
  603. }
  604. static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
  605. uint phy_mask,
  606. phy_interface_t interface)
  607. {
  608. int i;
  609. struct phy_device *phydev;
  610. phydev = search_for_existing_phy(bus, phy_mask, interface);
  611. if (phydev)
  612. return phydev;
  613. /* Try Standard (ie Clause 22) access */
  614. /* Otherwise we have to try Clause 45 */
  615. for (i = 0; i < 5; i++) {
  616. phydev = create_phy_by_mask(bus, phy_mask,
  617. i ? i : MDIO_DEVAD_NONE, interface);
  618. if (IS_ERR(phydev))
  619. return NULL;
  620. if (phydev)
  621. return phydev;
  622. }
  623. debug("\n%s PHY: ", bus->name);
  624. while (phy_mask) {
  625. int addr = ffs(phy_mask) - 1;
  626. debug("%d ", addr);
  627. phy_mask &= ~(1 << addr);
  628. }
  629. debug("not found\n");
  630. return NULL;
  631. }
  632. /**
  633. * get_phy_device - reads the specified PHY device and returns its
  634. * @phy_device struct
  635. * @bus: the target MII bus
  636. * @addr: PHY address on the MII bus
  637. *
  638. * Description: Reads the ID registers of the PHY at @addr on the
  639. * @bus, then allocates and returns the phy_device to represent it.
  640. */
  641. static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
  642. phy_interface_t interface)
  643. {
  644. return get_phy_device_by_mask(bus, 1 << addr, interface);
  645. }
  646. int phy_reset(struct phy_device *phydev)
  647. {
  648. int reg;
  649. int timeout = 500;
  650. int devad = MDIO_DEVAD_NONE;
  651. if (phydev->flags & PHY_FLAG_BROKEN_RESET)
  652. return 0;
  653. #ifdef CONFIG_PHYLIB_10G
  654. /* If it's 10G, we need to issue reset through one of the MMDs */
  655. if (is_10g_interface(phydev->interface)) {
  656. if (!phydev->mmds)
  657. gen10g_discover_mmds(phydev);
  658. devad = ffs(phydev->mmds) - 1;
  659. }
  660. #endif
  661. if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) {
  662. debug("PHY reset failed\n");
  663. return -1;
  664. }
  665. #ifdef CONFIG_PHY_RESET_DELAY
  666. udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
  667. #endif
  668. /*
  669. * Poll the control register for the reset bit to go to 0 (it is
  670. * auto-clearing). This should happen within 0.5 seconds per the
  671. * IEEE spec.
  672. */
  673. reg = phy_read(phydev, devad, MII_BMCR);
  674. while ((reg & BMCR_RESET) && timeout--) {
  675. reg = phy_read(phydev, devad, MII_BMCR);
  676. if (reg < 0) {
  677. debug("PHY status read failed\n");
  678. return -1;
  679. }
  680. udelay(1000);
  681. }
  682. if (reg & BMCR_RESET) {
  683. puts("PHY reset timed out\n");
  684. return -1;
  685. }
  686. return 0;
  687. }
  688. int miiphy_reset(const char *devname, unsigned char addr)
  689. {
  690. struct mii_dev *bus = miiphy_get_dev_by_name(devname);
  691. struct phy_device *phydev;
  692. /*
  693. * miiphy_reset was only used on standard PHYs, so we'll fake it here.
  694. * If later code tries to connect with the right interface, this will
  695. * be corrected by get_phy_device in phy_connect()
  696. */
  697. phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
  698. return phy_reset(phydev);
  699. }
  700. struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask,
  701. phy_interface_t interface)
  702. {
  703. /* Reset the bus */
  704. if (bus->reset) {
  705. bus->reset(bus);
  706. /* Wait 15ms to make sure the PHY has come out of hard reset */
  707. mdelay(15);
  708. }
  709. return get_phy_device_by_mask(bus, phy_mask, interface);
  710. }
  711. #ifdef CONFIG_DM_ETH
  712. void phy_connect_dev(struct phy_device *phydev, struct udevice *dev)
  713. #else
  714. void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
  715. #endif
  716. {
  717. /* Soft Reset the PHY */
  718. phy_reset(phydev);
  719. if (phydev->dev && phydev->dev != dev) {
  720. printf("%s:%d is connected to %s. Reconnecting to %s\n",
  721. phydev->bus->name, phydev->addr,
  722. phydev->dev->name, dev->name);
  723. }
  724. phydev->dev = dev;
  725. debug("%s connected to %s\n", dev->name, phydev->drv->name);
  726. }
  727. #ifdef CONFIG_DM_ETH
  728. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  729. struct udevice *dev,
  730. phy_interface_t interface)
  731. #else
  732. struct phy_device *phy_connect(struct mii_dev *bus, int addr,
  733. struct eth_device *dev,
  734. phy_interface_t interface)
  735. #endif
  736. {
  737. struct phy_device *phydev = NULL;
  738. #ifdef CONFIG_PHY_FIXED
  739. int sn;
  740. const char *name;
  741. sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
  742. while (sn > 0) {
  743. name = fdt_get_name(gd->fdt_blob, sn, NULL);
  744. if (name && strcmp(name, "fixed-link") == 0) {
  745. phydev = phy_device_create(bus,
  746. sn, PHY_FIXED_ID, interface);
  747. break;
  748. }
  749. sn = fdt_next_subnode(gd->fdt_blob, sn);
  750. }
  751. #endif
  752. if (!phydev)
  753. phydev = phy_find_by_mask(bus, 1 << addr, interface);
  754. if (phydev)
  755. phy_connect_dev(phydev, dev);
  756. else
  757. printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
  758. return phydev;
  759. }
  760. /*
  761. * Start the PHY. Returns 0 on success, or a negative error code.
  762. */
  763. int phy_startup(struct phy_device *phydev)
  764. {
  765. if (phydev->drv->startup)
  766. return phydev->drv->startup(phydev);
  767. return 0;
  768. }
  769. __weak int board_phy_config(struct phy_device *phydev)
  770. {
  771. if (phydev->drv->config)
  772. return phydev->drv->config(phydev);
  773. return 0;
  774. }
  775. int phy_config(struct phy_device *phydev)
  776. {
  777. /* Invoke an optional board-specific helper */
  778. return board_phy_config(phydev);
  779. }
  780. int phy_shutdown(struct phy_device *phydev)
  781. {
  782. if (phydev->drv->shutdown)
  783. phydev->drv->shutdown(phydev);
  784. return 0;
  785. }
  786. int phy_get_interface_by_name(const char *str)
  787. {
  788. int i;
  789. for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
  790. if (!strcmp(str, phy_interface_strings[i]))
  791. return i;
  792. }
  793. return -1;
  794. }