spl.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Technexion Ltd.
  4. *
  5. * Author: Richard Hu <richard.hu@technexion.com>
  6. */
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch-mx7/mx7-ddr.h>
  11. #include <asm/gpio.h>
  12. #include <spl.h>
  13. #if defined(CONFIG_SPL_BUILD)
  14. #ifdef CONFIG_SPL_OS_BOOT
  15. int spl_start_uboot(void)
  16. {
  17. return 0;
  18. }
  19. #endif
  20. static struct ddrc ddrc_regs_val = {
  21. .mstr = 0x01040001,
  22. .rfshtmg = 0x00400046,
  23. .init1 = 0x00690000,
  24. .init0 = 0x00020083,
  25. .init3 = 0x09300004,
  26. .init4 = 0x04080000,
  27. .init5 = 0x00100004,
  28. .rankctl = 0x0000033F,
  29. .dramtmg0 = 0x09081109,
  30. .dramtmg1 = 0x0007020d,
  31. .dramtmg2 = 0x03040407,
  32. .dramtmg3 = 0x00002006,
  33. .dramtmg4 = 0x04020205,
  34. .dramtmg5 = 0x03030202,
  35. .dramtmg8 = 0x00000803,
  36. .zqctl0 = 0x00800020,
  37. .dfitmg0 = 0x02098204,
  38. .dfitmg1 = 0x00030303,
  39. .dfiupd0 = 0x80400003,
  40. .dfiupd1 = 0x00100020,
  41. .dfiupd2 = 0x80100004,
  42. .addrmap4 = 0x00000F0F,
  43. .odtcfg = 0x06000604,
  44. .odtmap = 0x00000001,
  45. .rfshtmg = 0x00400046,
  46. .dramtmg0 = 0x09081109,
  47. .addrmap0 = 0x0000001f,
  48. .addrmap1 = 0x00080808,
  49. .addrmap4 = 0x00000f0f,
  50. .addrmap5 = 0x07070707,
  51. .addrmap6 = 0x0f0f0707,
  52. };
  53. static struct ddrc_mp ddrc_mp_val = {
  54. .pctrl_0 = 0x00000001,
  55. };
  56. static struct ddr_phy ddr_phy_regs_val = {
  57. .phy_con0 = 0x17420f40,
  58. .phy_con1 = 0x10210100,
  59. .phy_con4 = 0x00060807,
  60. .mdll_con0 = 0x1010007e,
  61. .drvds_con0 = 0x00000d6e,
  62. .cmd_sdll_con0 = 0x00000010,
  63. .offset_lp_con0 = 0x0000000f,
  64. .offset_rd_con0 = 0x08080808,
  65. .offset_wr_con0 = 0x08080808,
  66. };
  67. static struct mx7_calibration calib_param = {
  68. .num_val = 5,
  69. .values = {
  70. 0x0E407304,
  71. 0x0E447304,
  72. 0x0E447306,
  73. 0x0E447304,
  74. 0x0E447304,
  75. },
  76. };
  77. static void gpr_init(void)
  78. {
  79. struct iomuxc_gpr_base_regs *gpr_regs =
  80. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  81. writel(0x4F400005, &gpr_regs->gpr[1]);
  82. }
  83. static bool is_1g(void)
  84. {
  85. gpio_direction_input(IMX_GPIO_NR(1, 12));
  86. return !gpio_get_value(IMX_GPIO_NR(1, 12));
  87. }
  88. static void ddr_init(void)
  89. {
  90. if (is_1g())
  91. ddrc_regs_val.addrmap6 = 0x0f070707;
  92. mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
  93. &calib_param);
  94. }
  95. void board_init_f(ulong dummy)
  96. {
  97. arch_cpu_init();
  98. gpr_init();
  99. board_early_init_f();
  100. timer_init();
  101. preloader_console_init();
  102. ddr_init();
  103. memset(__bss_start, 0, __bss_end - __bss_start);
  104. board_init_r(NULL, 0);
  105. }
  106. void reset_cpu(ulong addr)
  107. {
  108. }
  109. #endif