ddr.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DDR_H__
  6. #define __DDR_H__
  7. struct board_specific_parameters {
  8. u32 n_ranks;
  9. u32 datarate_mhz_high;
  10. u32 rank_gb;
  11. u32 clk_adjust;
  12. u32 wrlvl_start;
  13. u32 wrlvl_ctl_2;
  14. u32 wrlvl_ctl_3;
  15. };
  16. /*
  17. * These tables contain all valid speeds we want to override with board
  18. * specific parameters. datarate_mhz_high values need to be in ascending order
  19. * for each n_ranks group.
  20. */
  21. static const struct board_specific_parameters udimm0[] = {
  22. /*
  23. * memory controller 0
  24. * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  25. * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  26. */
  27. {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
  28. {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
  29. {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
  30. {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
  31. {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
  32. {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a},
  33. {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09},
  34. {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a},
  35. {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a},
  36. {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09},
  37. {}
  38. };
  39. static const struct board_specific_parameters *udimms[] = {
  40. udimm0,
  41. };
  42. #endif