ddr.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. #include <asm/immap_85xx.h>
  8. #include <asm/processor.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <asm/io.h>
  12. #include <asm/fsl_law.h>
  13. /* CONFIG_SYS_DDR_RAW_TIMING */
  14. /*
  15. * Hynix H5TQ1G83TFR-H9C
  16. */
  17. dimm_params_t ddr_raw_timing = {
  18. .n_ranks = 1,
  19. .rank_density = 536870912u,
  20. .capacity = 536870912u,
  21. .primary_sdram_width = 32,
  22. .ec_sdram_width = 0,
  23. .registered_dimm = 0,
  24. .mirrored_dimm = 0,
  25. .n_row_addr = 14,
  26. .n_col_addr = 10,
  27. .n_banks_per_sdram_device = 8,
  28. .edc_config = 0,
  29. .burst_lengths_bitmask = 0x0c,
  30. .tckmin_x_ps = 1875,
  31. .caslat_x = 0x1e << 4, /* 5,6,7,8 */
  32. .taa_ps = 13125,
  33. .twr_ps = 18000,
  34. .trcd_ps = 13125,
  35. .trrd_ps = 7500,
  36. .trp_ps = 13125,
  37. .tras_ps = 37500,
  38. .trc_ps = 50625,
  39. .trfc_ps = 160000,
  40. .twtr_ps = 7500,
  41. .trtp_ps = 7500,
  42. .refresh_rate_ps = 7800000,
  43. .tfaw_ps = 37500,
  44. };
  45. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  46. unsigned int controller_number,
  47. unsigned int dimm_number)
  48. {
  49. const char dimm_model[] = "Fixed DDR on board";
  50. if ((controller_number == 0) && (dimm_number == 0)) {
  51. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  52. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  53. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  54. }
  55. return 0;
  56. }
  57. void fsl_ddr_board_options(memctl_options_t *popts,
  58. dimm_params_t *pdimm,
  59. unsigned int ctrl_num)
  60. {
  61. int i;
  62. popts->clk_adjust = 6;
  63. popts->cpo_override = 0x1f;
  64. popts->write_data_delay = 2;
  65. popts->half_strength_driver_enable = 1;
  66. /* Write leveling override */
  67. popts->wrlvl_en = 1;
  68. popts->wrlvl_override = 1;
  69. popts->wrlvl_sample = 0xf;
  70. popts->wrlvl_start = 0x8;
  71. popts->trwt_override = 1;
  72. popts->trwt = 0;
  73. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  74. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  75. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  76. }
  77. }