fsl_ddr.h 4.8 KB

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  1. /*
  2. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef FSL_DDR_MAIN_H
  7. #define FSL_DDR_MAIN_H
  8. #include <fsl_ddrc_version.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <fsl_ddr_dimm_params.h>
  11. #include <common_timing_params.h>
  12. #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  13. /* All controllers are for main memory */
  14. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
  15. #endif
  16. #ifdef CONFIG_SYS_FSL_DDR_LE
  17. #define ddr_in32(a) in_le32(a)
  18. #define ddr_out32(a, v) out_le32(a, v)
  19. #define ddr_setbits32(a, v) setbits_le32(a, v)
  20. #define ddr_clrbits32(a, v) clrbits_le32(a, v)
  21. #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  22. #else
  23. #define ddr_in32(a) in_be32(a)
  24. #define ddr_out32(a, v) out_be32(a, v)
  25. #define ddr_setbits32(a, v) setbits_be32(a, v)
  26. #define ddr_clrbits32(a, v) clrbits_be32(a, v)
  27. #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  28. #endif
  29. u32 fsl_ddr_get_version(unsigned int ctrl_num);
  30. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  31. /*
  32. * Bind the main DDR setup driver's generic names
  33. * to this specific DDR technology.
  34. */
  35. static __inline__ int
  36. compute_dimm_parameters(const unsigned int ctrl_num,
  37. const generic_spd_eeprom_t *spd,
  38. dimm_params_t *pdimm,
  39. unsigned int dimm_number)
  40. {
  41. return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  42. }
  43. #endif
  44. /*
  45. * Data Structures
  46. *
  47. * All data structures have to be on the stack
  48. */
  49. #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
  50. #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  51. typedef struct {
  52. generic_spd_eeprom_t
  53. spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  54. struct dimm_params_s
  55. dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  56. memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  57. common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  58. fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  59. unsigned int first_ctrl;
  60. unsigned int num_ctrls;
  61. unsigned long long mem_base;
  62. unsigned int dimm_slots_per_ctrl;
  63. int (*board_need_mem_reset)(void);
  64. void (*board_mem_reset)(void);
  65. void (*board_mem_de_reset)(void);
  66. } fsl_ddr_info_t;
  67. /* Compute steps */
  68. #define STEP_GET_SPD (1 << 0)
  69. #define STEP_COMPUTE_DIMM_PARMS (1 << 1)
  70. #define STEP_COMPUTE_COMMON_PARMS (1 << 2)
  71. #define STEP_GATHER_OPTS (1 << 3)
  72. #define STEP_ASSIGN_ADDRESSES (1 << 4)
  73. #define STEP_COMPUTE_REGS (1 << 5)
  74. #define STEP_PROGRAM_REGS (1 << 6)
  75. #define STEP_ALL 0xFFF
  76. unsigned long long
  77. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  78. unsigned int size_only);
  79. const char *step_to_string(unsigned int step);
  80. unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  81. const memctl_options_t *popts,
  82. fsl_ddr_cfg_regs_t *ddr,
  83. const common_timing_params_t *common_dimm,
  84. const dimm_params_t *dimm_parameters,
  85. unsigned int dbw_capacity_adjust,
  86. unsigned int size_only);
  87. unsigned int compute_lowest_common_dimm_parameters(
  88. const unsigned int ctrl_num,
  89. const dimm_params_t *dimm_params,
  90. common_timing_params_t *outpdimm,
  91. unsigned int number_of_dimms);
  92. unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  93. memctl_options_t *popts,
  94. dimm_params_t *pdimm,
  95. unsigned int ctrl_num);
  96. void check_interleaving_options(fsl_ddr_info_t *pinfo);
  97. unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
  98. unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
  99. unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
  100. void fsl_ddr_set_lawbar(
  101. const common_timing_params_t *memctl_common_params,
  102. unsigned int memctl_interleaved,
  103. unsigned int ctrl_num);
  104. void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
  105. unsigned int last_ctrl);
  106. int fsl_ddr_interactive_env_var_exists(void);
  107. unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
  108. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  109. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  110. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
  111. unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
  112. void board_add_ram_info(int use_default);
  113. /* processor specific function */
  114. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  115. unsigned int ctrl_num, int step);
  116. void remove_unused_controllers(fsl_ddr_info_t *info);
  117. /* board specific function */
  118. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  119. unsigned int controller_number,
  120. unsigned int dimm_number);
  121. void update_spd_address(unsigned int ctrl_num,
  122. unsigned int slot,
  123. unsigned int *addr);
  124. void erratum_a009942_check_cpo(void);
  125. #endif