ls2080a_stream_id.h 2.7 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. */
  7. #ifndef __FSL_STREAM_ID_H
  8. #define __FSL_STREAM_ID_H
  9. /*
  10. * Stream IDs on ls2080a devices are not hardwired and are
  11. * programmed by sw. There are a limited number of stream IDs
  12. * available, and the partitioning of them is scenario dependent.
  13. * This header defines the partitioning between legacy, PCI,
  14. * and DPAA2 devices.
  15. *
  16. * This partitioning can be customized in this file depending
  17. * on the specific hardware config:
  18. *
  19. * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
  20. * -all legacy devices get a unique stream ID assigned and programmed in
  21. * their AMQR registers by u-boot
  22. *
  23. * -PCIe
  24. * -there is a range of stream IDs set aside for PCI in this
  25. * file. U-boot will scan the PCI bus and for each device discovered:
  26. * -allocate a streamID
  27. * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
  28. * -set a msi-map entry in the PEXn controller node in the
  29. * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
  30. * for more info on the msi-map definition)
  31. *
  32. * -DPAA2
  33. * -u-boot will allocate a range of stream IDs to be used by the Management
  34. * Complex for containers and will set these values in the MC DPC image.
  35. * -the MC is responsible for allocating and setting up 'isolation context
  36. * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
  37. *
  38. * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for
  39. * each of the different bus masters. The relationship between
  40. * the AMQ registers and stream IDs is defined in the table below:
  41. * AMQ bit streamID bit
  42. * ---------------------------
  43. * PL[18] 9 // privilege bit
  44. * BMT[17] 8 // bypass translation
  45. * VA[16] 7 // reserved
  46. * [15] - // unused
  47. * ICID[14:7] - // unused
  48. * ICID[6:0] 6-0 // isolation context id
  49. * ----------------------------
  50. *
  51. */
  52. #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
  53. #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
  54. #define FSL_INVALID_STREAM_ID 0
  55. #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
  56. /* legacy devices */
  57. #define FSL_USB1_STREAM_ID 1
  58. #define FSL_USB2_STREAM_ID 2
  59. #define FSL_SDMMC_STREAM_ID 3
  60. #define FSL_SATA1_STREAM_ID 4
  61. #define FSL_SATA2_STREAM_ID 5
  62. #define FSL_DMA_STREAM_ID 6
  63. /* PCI - programmed in PEXn_LUT */
  64. #define FSL_PEX_STREAM_ID_START 7
  65. #define FSL_PEX_STREAM_ID_END 22
  66. /* DPAA2 - set in MC DPC and alloced by MC */
  67. #define FSL_DPAA2_STREAM_ID_START 23
  68. #define FSL_DPAA2_STREAM_ID_END 63
  69. #endif