ddr.c 3.6 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <hwconfig.h>
  9. #include <asm/mmu.h>
  10. #include <fsl_ddr_sdram.h>
  11. #include <fsl_ddr_dimm_params.h>
  12. #include <asm/fsl_law.h>
  13. #include <asm/mpc85xx_gpio.h>
  14. #include "ddr.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  17. unsigned int controller_number,
  18. unsigned int dimm_number)
  19. {
  20. const char dimm_model[] = "RAW timing DDR";
  21. if ((controller_number == 0) && (dimm_number == 0)) {
  22. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  23. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  24. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  25. }
  26. return 0;
  27. }
  28. void fsl_ddr_board_options(memctl_options_t *popts,
  29. dimm_params_t *pdimm,
  30. unsigned int ctrl_num)
  31. {
  32. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  33. ulong ddr_freq;
  34. if (ctrl_num > 1) {
  35. printf("Not supported controller number %d\n", ctrl_num);
  36. return;
  37. }
  38. if (!pdimm->n_ranks)
  39. return;
  40. pbsp = udimms[0];
  41. /* Get clk_adjust according to the board ddr
  42. * freqency and n_banks specified in board_specific_parameters table.
  43. */
  44. ddr_freq = get_ddr_freq(0) / 1000000;
  45. while (pbsp->datarate_mhz_high) {
  46. if (pbsp->n_ranks == pdimm->n_ranks &&
  47. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  48. if (ddr_freq <= pbsp->datarate_mhz_high) {
  49. popts->clk_adjust = pbsp->clk_adjust;
  50. popts->wrlvl_start = pbsp->wrlvl_start;
  51. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  52. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  53. goto found;
  54. }
  55. pbsp_highest = pbsp;
  56. }
  57. pbsp++;
  58. }
  59. if (pbsp_highest) {
  60. printf("Error: board specific timing not found\n");
  61. printf("for data rate %lu MT/s\n", ddr_freq);
  62. printf("Trying to use the highest speed (%u) parameters\n",
  63. pbsp_highest->datarate_mhz_high);
  64. popts->clk_adjust = pbsp_highest->clk_adjust;
  65. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  66. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  67. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  68. } else {
  69. panic("DIMM is not supported by this board");
  70. }
  71. found:
  72. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  73. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  74. "wrlvl_ctrl_3 0x%x\n",
  75. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  76. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  77. pbsp->wrlvl_ctl_3);
  78. /*
  79. * Factors to consider for half-strength driver enable:
  80. * - number of DIMMs installed
  81. */
  82. popts->half_strength_driver_enable = 0;
  83. /*
  84. * Write leveling override
  85. */
  86. popts->wrlvl_override = 1;
  87. popts->wrlvl_sample = 0xf;
  88. /*
  89. * rtt and rtt_wr override
  90. */
  91. popts->rtt_override = 0;
  92. /* Enable ZQ calibration */
  93. popts->zq_en = 1;
  94. /* DHC_EN =1, ODT = 75 Ohm */
  95. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  96. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  97. }
  98. #if defined(CONFIG_DEEP_SLEEP)
  99. void board_mem_sleep_setup(void)
  100. {
  101. void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
  102. /* does not provide HW signals for power management */
  103. clrbits_8(cpld_base + 0x17, 0x40);
  104. /* Disable MCKE isolation */
  105. gpio_set_value(2, 0);
  106. udelay(1);
  107. }
  108. #endif
  109. phys_size_t initdram(int board_type)
  110. {
  111. phys_size_t dram_size;
  112. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  113. puts("Initializing....using SPD\n");
  114. dram_size = fsl_ddr_sdram();
  115. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  116. dram_size *= 0x100000;
  117. #else
  118. dram_size = fsl_ddr_sdram_size();
  119. #endif
  120. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  121. fsl_dp_resume();
  122. #endif
  123. return dram_size;
  124. }