Sergey Temerkhanov
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94f7ff36e5
armv8: New MMU setup code allowing to use 48+ bits PA/VA
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%!s(int64=9) %!d(string=hai) anos |
Alison Wang
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d764129d30
armv8/layerscape: Update MMU table with execute-never bits
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%!s(int64=9) %!d(string=hai) anos |
Mingkai Hu
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8281c58fd4
armv8/fsl_lsch2: Add fsl_lsch2 SoC
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%!s(int64=9) %!d(string=hai) anos |
Thierry Reding
|
ad3d6e88a1
armv8/mmu: Set bits marked RES1 in TCR
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%!s(int64=9) %!d(string=hai) anos |
Thierry Reding
|
55aa0bed98
armv8/mmu: Clean up TCR programming
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%!s(int64=9) %!d(string=hai) anos |
Alison Wang
|
9979922015
armv8: fsl-lsch3: Rewrite MMU translation table entries
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%!s(int64=9) %!d(string=hai) anos |
Zhichun Hua
|
21a257b9b3
armv8: Fix TCR macros for shareability attribute
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%!s(int64=10) %!d(string=hai) anos |
York Sun
|
6c747f4ad4
armv8/fsl-lsch3: Change normal memory shareability
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%!s(int64=10) %!d(string=hai) anos |
York Sun
|
22932ffc03
ARMv8: Adjust MMU setup
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%!s(int64=11) %!d(string=hai) anos |
David Feng
|
0ae7653128
arm64: core support
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%!s(int64=11) %!d(string=hai) anos |