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Árbore: ad3d6e88a1
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Commit History

Autor SHA1 Mensaxe Data
  Thierry Reding ad3d6e88a1 armv8/mmu: Set bits marked RES1 in TCR %!s(int64=9) %!d(string=hai) anos
  Alison Wang 9979922015 armv8: fsl-lsch3: Rewrite MMU translation table entries %!s(int64=9) %!d(string=hai) anos
  Wu, Josh 633b6ccedf ARM: cache: implement a default weak flush_cache() function %!s(int64=9) %!d(string=hai) anos
  Wu, Josh 387871a10e ARM: cache: add an empty stub function for invalidate/flush dcache %!s(int64=9) %!d(string=hai) anos
  Siva Durga Prasad Paladugu dad17fd510 armv8: caches: Added routine to set non cacheable region %!s(int64=10) %!d(string=hai) anos
  Thierry Reding 8b19dff579 armv8/cache: Fix page table creation %!s(int64=10) %!d(string=hai) anos
  York Sun dcd468b8f4 armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack %!s(int64=10) %!d(string=hai) anos
  York Sun 2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC %!s(int64=11) %!d(string=hai) anos
  York Sun 22932ffc03 ARMv8: Adjust MMU setup %!s(int64=11) %!d(string=hai) anos
  York Sun 1e6ad55c05 armv8/cache: Change cache invalidate and flush function %!s(int64=11) %!d(string=hai) anos
  York Sun f5222cfd49 armv8/cache: Consolidate setting for MAIR and TCR %!s(int64=11) %!d(string=hai) anos
  David Feng 0ae7653128 arm64: core support %!s(int64=11) %!d(string=hai) anos