 Daniel Schwierzeck
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46203baf66
MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE
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%!s(int64=6) %!d(string=hai) anos |
|
Daniel Schwierzeck
|
5ef337a037
MIPS: cache: make index base address configurable
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%!s(int64=6) %!d(string=hai) anos |
|
Daniel Schwierzeck
|
b838586086
MIPS: cache: optimise changing of k0 CCA mode
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%!s(int64=6) %!d(string=hai) anos |
|
Daniel Schwierzeck
|
2f85c2be21
MIPS: cache: reimplement dcache_[status, enable, disable]
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%!s(int64=6) %!d(string=hai) anos |
 Tom Rini
|
83d290c56f
SPDX: Convert all of our single license tags to Linux Kernel style
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%!s(int64=7) %!d(string=hai) anos |
 Paul Burton
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639200f6a0
MIPS: Ensure cache ops complete in mips_cache_reset
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
d608254b0a
MIPS: Clear hazard between TagLo writes & cache ops
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
7953354b07
MIPS: Join the coherent domain when a CM is present
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
4baa0ab67d
MIPS: L2 cache support
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%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
5c72e5a62e
MIPS: Define register names for cache init
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
33b5c9b209
MIPS: Enable use of the instruction cache earlier
|
%!s(int64=8) %!d(string=hai) anos |
|
Paul Burton
|
372286217f
MIPS: Split I & D cache line size config
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%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
ace3be4f15
MIPS: Move cache sizes to Kconfig
|
%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
9f8ac82452
MIPS: Use unchecked immediate addition/subtraction
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%!s(int64=9) %!d(string=hai) anos |
|
Daniel Schwierzeck
|
a3ab2ae7f6
MIPS: sync processor and register definitions with linux-4.4
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%!s(int64=9) %!d(string=hai) anos |
|
Paul Burton
|
8755d50706
MIPS: clear TagLo select 2 during cache init
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%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
dd7c72006e
MIPS: allow systems to skip loads during cache init
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%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
ca4e833cd6
MIPS: inline mips_init_[id]cache functions
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%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
ac22feca11
MIPS: refactor cache loops to a macro
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
536cb7ce1a
MIPS: refactor L1 cache config reads to a macro
|
%!s(int64=10) %!d(string=hai) anos |
|
Paul Burton
|
4a5d8898bc
MIPS: unify cache initialization code
|
%!s(int64=10) %!d(string=hai) anos |
