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U-Boot-1_2_0
U-Boot-1_1_6
U-Boot-1_1_5
LABEL_2006_06_30_2020
LABEL_2006_05_19_1133
LABEL_2006_05_10_1800
LABEL_2006_04_18_1106
LABEL_2006_03_12_0025
U-Boot-1_1_4
DENX-2005-10-29-2350
LABEL_2005_09_15_2320
U-Boot-1_1_3
LABEL_2005_08_12_0050
LABEL_2005_07_04_0202
LABEL_2005_05_13_0050
LABEL_2005_05_09_1245
LABEL_2005_05_05_1920
LABEL_2005_04_14_0115
LABEL_2005_04_05_2345
LABEL_2005_04_05_1830
LABEL_2005_03_15_0125
LABEL_2005_03_06_0225
LABEL_2005_02_28_0050
LABEL_2005_02_08_1615
LABEL_2005_02_07_2045
LABEL_2005_01_31_2245
U-Boot-1_1_2
LABEL_2004_12_20_1220
LABEL_2004_12_19_2240
LABEL_2004_12_19_1100
LABEL_2004_12_18_2335
LABEL_2004_11_25_0035
LABEL_2004_11_17_2222
LABEL_2004_10_20_0020
LABEL_2004_10_12_0110
LABEL_2004_09_09_0000
LABEL_2004_08_29_0045
LABEL_2004_08_28_2355
LABEL_2004_07_01_1200
LABEL_2004_06_24_1800
LABEL_2004_05_29_1850
LABEL_2004_05_19_2335
U-Boot-1_1_1
LABEL_2004_04_23_2240
LABEL_2004_04_18_2135
U-Boot-1_1_0
LABEL_2004_03_25_1630
LABEL_2004_03_16_2330
LABEL_2004_03_14_2340
LABEL_2004_03_12_0130
LABEL_2004_02_24_0305
LABEL_2004_02_20_2310
U-Boot-1_0_2
LABEL_2004_02_11_2240
LABEL_2004_01_21_2110
LABEL_2004_01_29_1030
U-Boot-1_0_1
LABEL_2003_12_06_1550
LABEL_2003_11_26_MKR
U-Boot-1_0_0
LABEL_2003_10_20_0025
LABEL_2003_10_16_0200
LABEL_2003_10_14_2140
LABEL_2003_10_10_1200
LABEL_2003_10_09_2320
LABEL_2003_10_09_1515
LABEL_2003_10_06_2355
LABEL_2003_10_01_1830
LABEL_2003_09_18_2045
LABEL_2003_09_16_2310
LABEL_2003_09_13_2100
LABEL_2003_09_12_1745
LABEL_2003_09_12_0110
U-Boot-0_4_8
LABEL_2003_09_06_0055
U-Boot-0_4_7
U-Boot-0_4_6
U-Boot-0_4_5
U-Boot-0_4_4
U-Boot-0_4_3
U-Boot-0_4_2
U-Boot-0_4_1
LABEL_2003_06_29_0145
LABEL_2003_06_28_1800-stable
LABEL_2003_06_28_0130-stable
LABEL_2003_06_28_0050-stable
LABEL_2003_06_27_2340
U-Boot-0_4_0
LABEL_2003_06_26_2220
LABEL_2003_06_22_1530
LABEL_2003_06_16_0055
LABEL_2003_06_05_2140
LABEL_2003_06_04_0200
LABEL_2003_05_31_2115
LABEL_2003_05_30_1450
LABEL_2003_05_23_1450
LABEL_2003_05_23_0055
LABEL_2003_05_22_2230
LABEL_2003_05_20_2250
LABEL_2003_05_20_1630
LABEL_2003_05_12_2355
LABEL_2003_05_03_1700
U-Boot-0_3_1
LABEL_2003_04_15_1900
U-Boot-0_3_0
LABEL_2003_04_05_0300
LABEL_2003_03_27_1900
LABEL_2003_03_26_1300
LABEL_2003_03_25_1830
LABEL_2003_03_14_2150
LABEL_2003_03_06_2255
LABEL_2003_03_06_1440
LABEL_2003_03_06_0200
LABEL_2003_03_06_0050
LABEL_2003_02_28_0150
LABEL_2003_01_14_0055
LABEL_2003_01_11_1050
LABEL_2002_12_28_1700
LABEL_2002_12_21_0040
U-Boot-0_2_0
LABEL_2002_12_07_0120
LABEL_2002_12_03_2230
LABEL_2002_11_22_0015
LABEL_2002_11_18_0115
LABEL_2002_11_11_2211
LABEL_2002_11_10_2310
LABEL_2002_11_05_1735
LABEL_2002_11_05_0120
U_BOOT_0_1_0
Historial de Commits
| Autor | SHA1 Mensaje | Fecha |
|---|---|---|
 Dave Liu
|
b4983e16d1 fsl-ddr: use the 1T timing as default configuration | hace 16 años |
 Haiying Wang
|
dfb49108e4 Pass dimm parameters to populate populate controller options | hace 16 años |
 Kumar Gala
|
0e7927db13 FSL DDR: Convert STXSSA to new DDR code. | hace 17 años |