 Alison Wang
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7c5e1feb1d
armv8: aarch64: Fix the warning about x1-x3 nonzero issue
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%!s(int64=8) %!d(string=hai) anos |
 macro.wave.z@gmail.com
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9a561753ce
ARMv8: Setup PSCI memory and device tree
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%!s(int64=8) %!d(string=hai) anos |
|
Alison Wang
|
3db86f4bbd
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled
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%!s(int64=8) %!d(string=hai) anos |
|
Alison Wang
|
ec6617c397
armv8: Support loading 32-bit OS in AArch32 execution state
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%!s(int64=8) %!d(string=hai) anos |
 Keerthy
|
06d43c808d
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
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%!s(int64=8) %!d(string=hai) anos |
 Stephen Warren
|
1ab557a074
armv8: add hooks for all cache-wide operations
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%!s(int64=8) %!d(string=hai) anos |
 Alexander Graf
|
3ee655ed83
arm: Add PSCI shutdown function
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%!s(int64=8) %!d(string=hai) anos |
|
Alexander Graf
|
51bfb5b6f5
arm: Disable HVC PSCI calls by default
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%!s(int64=8) %!d(string=hai) anos |
|
Keerthy
|
d31d4a2d75
ARM: Introduce function to switch to hypervisor mode
|
%!s(int64=8) %!d(string=hai) anos |
 Tom Rini
|
a78cd86132
ARM: Rework and correct barrier definitions
|
%!s(int64=8) %!d(string=hai) anos |
 Beniamino Galvani
|
5a07abb370
arm: implement generic PSCI reset call for armv8
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%!s(int64=9) %!d(string=hai) anos |
|
Alexander Graf
|
d990f5c834
arm: Add support for HYP mode and LPAE page tables
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%!s(int64=9) %!d(string=hai) anos |
|
Alexander Graf
|
53eb45ef40
arm64: Add 32bit arm compatible dcache definitions
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%!s(int64=9) %!d(string=hai) anos |
|
Alexander Graf
|
7985cdf74b
arm64: Remove non-full-va map code
|
%!s(int64=9) %!d(string=hai) anos |
|
Alexander Graf
|
5e2ec773bb
arm64: Make full va map code more dynamic
|
%!s(int64=9) %!d(string=hai) anos |
 Marek Vasut
|
8890c2fbe6
arm: Remove S bit from MMU section entry
|
%!s(int64=9) %!d(string=hai) anos |
|
Marek Vasut
|
a592e6fb7f
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7
|
%!s(int64=9) %!d(string=hai) anos |
 Sergey Temerkhanov
|
a5b9fa30ce
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure
|
%!s(int64=9) %!d(string=hai) anos |
|
Sergey Temerkhanov
|
94f7ff36e5
armv8: New MMU setup code allowing to use 48+ bits PA/VA
|
%!s(int64=9) %!d(string=hai) anos |
|
Sergey Temerkhanov
|
ba5648cd91
armv8: Add read_mpidr() function
|
%!s(int64=9) %!d(string=hai) anos |
|
Stephen Warren
|
88f965d720
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY
|
%!s(int64=9) %!d(string=hai) anos |
|
Alison Wang
|
53fd4b8c22
arm: mmu: Add missing volatile for reading SCTLR register
|
%!s(int64=9) %!d(string=hai) anos |
 Siva Durga Prasad Paladugu
|
dad17fd510
armv8: caches: Added routine to set non cacheable region
|
%!s(int64=10) %!d(string=hai) anos |
 Simon Glass
|
5519912164
arm: Add a prototype for save_boot_params_ret()
|
%!s(int64=10) %!d(string=hai) anos |
 Ian Campbell
|
73169874a2
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0
|
%!s(int64=10) %!d(string=hai) anos |
 Bryan Brinsko
|
97840b5d1f
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
|
%!s(int64=10) %!d(string=hai) anos |
 York Sun
|
dcd468b8f4
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack
|
%!s(int64=10) %!d(string=hai) anos |
|
Simon Glass
|
e11c6c279d
arm: Allow lr to be saved by board code
|
%!s(int64=10) %!d(string=hai) anos |
 Thierry Reding
|
1dfdd9ba4e
ARM: Implement non-cached memory support
|
%!s(int64=10) %!d(string=hai) anos |
|
Thierry Reding
|
25026fa9f1
ARM: cache-cp15: Use more accurate types
|
%!s(int64=10) %!d(string=hai) anos |
