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U-Boot-1_2_0
U-Boot-1_1_6
U-Boot-1_1_5
LABEL_2006_06_30_2020
LABEL_2006_05_19_1133
LABEL_2006_05_10_1800
LABEL_2006_04_18_1106
LABEL_2006_03_12_0025
U-Boot-1_1_4
DENX-2005-10-29-2350
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U-Boot-1_1_3
LABEL_2005_08_12_0050
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U-Boot-1_1_1
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U-Boot-1_1_0
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U-Boot-1_0_2
LABEL_2004_02_11_2240
LABEL_2004_01_21_2110
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U-Boot-1_0_1
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LABEL_2003_11_26_MKR
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U-Boot-0_4_8
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U-Boot-0_4_6
U-Boot-0_4_5
U-Boot-0_4_4
U-Boot-0_4_3
U-Boot-0_4_2
U-Boot-0_4_1
LABEL_2003_06_29_0145
LABEL_2003_06_28_1800-stable
LABEL_2003_06_28_0130-stable
LABEL_2003_06_28_0050-stable
LABEL_2003_06_27_2340
U-Boot-0_4_0
LABEL_2003_06_26_2220
LABEL_2003_06_22_1530
LABEL_2003_06_16_0055
LABEL_2003_06_05_2140
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LABEL_2003_05_20_2250
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LABEL_2003_05_12_2355
LABEL_2003_05_03_1700
U-Boot-0_3_1
LABEL_2003_04_15_1900
U-Boot-0_3_0
LABEL_2003_04_05_0300
LABEL_2003_03_27_1900
LABEL_2003_03_26_1300
LABEL_2003_03_25_1830
LABEL_2003_03_14_2150
LABEL_2003_03_06_2255
LABEL_2003_03_06_1440
LABEL_2003_03_06_0200
LABEL_2003_03_06_0050
LABEL_2003_02_28_0150
LABEL_2003_01_14_0055
LABEL_2003_01_11_1050
LABEL_2002_12_28_1700
LABEL_2002_12_21_0040
U-Boot-0_2_0
LABEL_2002_12_07_0120
LABEL_2002_12_03_2230
LABEL_2002_11_22_0015
LABEL_2002_11_18_0115
LABEL_2002_11_11_2211
LABEL_2002_11_10_2310
LABEL_2002_11_05_1735
LABEL_2002_11_05_0120
U_BOOT_0_1_0
Historique des commits
| Auteur | SHA1 Message | Date |
|---|---|---|
 Chris Packham
|
672e559830 ddr: marvell: update ddr controller init and freq | il y a 7 ans |
|
Chris Packham
|
2efd27f76a ddr: marvell: use correct TREFI value | il y a 7 ans |
|
Chris Packham
|
dbaf09590d ddr: marvell: only assert M_ODT[0] on write for a single CS | il y a 7 ans |
 Marek Behún
|
90bcc3d38d driver/ddr: Add support for setting timing in hws_topology_map | il y a 8 ans |
 Robert P. J. Day
|
fc0b5948e0 Various, accumulated typos collected from around the tree. | il y a 8 ans |
 Stefan Roese
|
f1df936445 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr | il y a 10 ans |