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U-Boot-1_2_0
U-Boot-1_1_6
U-Boot-1_1_5
LABEL_2006_06_30_2020
LABEL_2006_05_19_1133
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U-Boot-1_1_4
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U_BOOT_0_1_0
Commit History
| Author | SHA1 Message | Date |
|---|---|---|
 Chris Packham
|
672e559830 ddr: marvell: update ddr controller init and freq | 7 years ago |
|
Chris Packham
|
2efd27f76a ddr: marvell: use correct TREFI value | 7 years ago |
|
Chris Packham
|
dbaf09590d ddr: marvell: only assert M_ODT[0] on write for a single CS | 7 years ago |
 Marek Behún
|
90bcc3d38d driver/ddr: Add support for setting timing in hws_topology_map | 8 years ago |
 Robert P. J. Day
|
fc0b5948e0 Various, accumulated typos collected from around the tree. | 8 years ago |
 Stefan Roese
|
f1df936445 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr | 10 years ago |