História revízii

Autor SHA1 Správa Dátum
  Tom Rini 83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style 7 rokov pred
  Tom Rini d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR 7 rokov pred
  Philipp Tomsich 35a69a3b01 rockchip: clk: rk3368: handle clk_enable requests for GMAC 7 rokov pred
  Philipp Tomsich 75b381aae8 rockchip: clk: guard set_parent implementations against OF_PLATDATA 7 rokov pred
  David Wu 64a12202ed clk: rockchip: clk_rk3368: Implement "assign-clock-parent" 7 rokov pred
  Elaine Zhang 538f67c332 rockchip: clk: bind reset driver 7 rokov pred
  Kever Yang f24e36dac3 rockchip: clock: update sysreset driver binding 7 rokov pred
  Masahiro Yamada 9b643e312d treewide: replace with error() with pr_err() 7 rokov pred
  David Wu 615514c16d rockchip: clk: Add rk3368 SARADC clock support 7 rokov pred
  Philipp Tomsich 9a342f48a6 rockchip: clk: rk3368: Convert to livetree 7 rokov pred
  Simon Glass c20ee0ed07 dtoc: Add support for 32 or 64-bit addresses 7 rokov pred
  Kever Yang 217273cd44 rockchip: clk: remove RATE_TO_DIV 8 rokov pred
  Philipp Tomsich cf8aceb1c9 rockchip: clk: rk3368: add support for configuring the SPI clocks 8 rokov pred
  Philipp Tomsich 4e4c40df30 rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate() 8 rokov pred
  Philipp Tomsich df0ae00041 rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock 8 rokov pred
  Philipp Tomsich 6292469073 rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL) 8 rokov pred
  Philipp Tomsich f5a432959a rockchip: clk: rk3368: implement MMC/SD clock reparenting 8 rokov pred
  Philipp Tomsich a00dfa042d rockchip: clk: rk3368: implement DPLL (DRAM PLL) support 8 rokov pred
  Philipp Tomsich 4bebf94e85 rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM 8 rokov pred
  Philipp Tomsich bee6180126 rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver 8 rokov pred
  Philipp Tomsich ddfe77df15 rockchip: clk: rk3368: implement bandwidth adjust for PLLs 8 rokov pred
  Philipp Tomsich cdc6080a28 rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc 8 rokov pred
  Andy Yan d1dcf8527e rockchip: rk3368: Add clock driver 8 rokov pred