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@@ -10,6 +10,13 @@
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#include <asm/irq.h>
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#include <asm/mrccache.h>
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#include <asm/post.h>
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+#include <asm/arch/iomap.h>
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+
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+/* GPIO SUS */
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+#define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
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+#define GPIO_SUS_DFX5_CONF0 0x150
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+#define BYT_TRIG_LVL BIT(24)
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+#define BYT_TRIG_POS BIT(25)
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#ifndef CONFIG_EFI_APP
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int arch_cpu_init(void)
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@@ -33,6 +40,21 @@ int arch_misc_init(void)
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mrccache_save();
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#endif
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+ /*
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+ * For some unknown reason, FSP (gold4) for BayTrail configures
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+ * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
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+ * This does not cause any issue when Linux kernel runs w/ or w/o
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+ * the pinctrl driver for BayTrail. However this causes unstable
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+ * S3 resume if the pinctrl driver is included in the kernel build.
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+ * As this pin keeps generating interrupts during an S3 resume,
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+ * and there is no IRQ requester in the kernel to handle it, the
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+ * kernel seems to hang and does not continue resuming.
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+ *
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+ * Clear the mysterious interrupt bits for this pin.
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+ */
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+ clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
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+ BYT_TRIG_LVL | BYT_TRIG_POS);
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+
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return 0;
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}
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