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@@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void)
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/* Set PLL clock receiver to LVPECL */
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
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- if (check_error())
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+ if (check_error()) {
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+ printf("ERROR: failed to set PCIe reference clock receiver --"
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+ "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
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+
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return -1;
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+ }
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+
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+ /* Did resistance calibration work? */
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+ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
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+ printf("ERROR: PCIe resistance calibration failed --"
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+ "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
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- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
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- {
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- printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
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- SDR_READ(PESDR0_PLLLCT2));
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return -1;
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}
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/* De-assert reset of PCIe PLL, wait for lock */
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SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
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- udelay(3);
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+ udelay(300); /* 300 uS is maximum time lock should take */
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while (time_out) {
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if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
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time_out--;
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- udelay(1);
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+ udelay(20); /* Wait 20 uS more if needed */
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} else
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break;
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}
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if (!time_out) {
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- printf("PCIE: VCO output not locked\n");
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+ printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
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+ "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
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+
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return -1;
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}
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return 0;
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