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@@ -11,6 +11,7 @@
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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+#include <asm/errno.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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@@ -293,7 +294,8 @@ int config_serdes1_refclks(void)
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 serdes1_prtcl, lane;
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unsigned int flag_sgmii_aurora_prtcl = 0;
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- int ret, i;
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+ int i;
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+ int ret = 0;
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serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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@@ -304,10 +306,12 @@ int config_serdes1_refclks(void)
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serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
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- /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
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+ /* To prevent generation of reset request from SerDes
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+ * while changing the refclks, By setting SRDS_RST_MSK bit,
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+ * SerDes reset event cannot cause a reset request
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*/
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- for (i = 0; i < PLL_NUM; i++)
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- clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
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+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
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+
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/* Reconfigure IDT idt8t49n222a device for CPRI to work
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* For this SerDes1's Refclk1 and refclk2 need to be set
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* to 122.88MHz
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@@ -345,11 +349,11 @@ int config_serdes1_refclks(void)
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SERDES_REFCLK_122_88, 0);
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if (ret) {
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printf("IDT8T49N222A configuration failed.\n");
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- return ret;
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+ goto out;
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} else
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- printf("IDT8T49N222A configured.\n");
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+ debug("IDT8T49N222A configured.\n");
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} else {
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- return ret;
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+ goto out;
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}
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select_i2c_ch_pca(I2C_CH_DEFAULT);
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@@ -400,16 +404,99 @@ int config_serdes1_refclks(void)
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printf("WARNING:IDT8T49N222A configuration not"
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" supported for:%x SerDes1 Protocol.\n",
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serdes1_prtcl);
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- return -1;
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}
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- return 0;
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+out:
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+ /* Clearing SRDS_RST_MSK bit as now
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+ * SerDes reset event can cause a reset request
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+ */
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+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
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+ return ret;
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+}
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+
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+int config_serdes2_refclks(void)
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+{
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+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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+ serdes_corenet_t *srds2_regs =
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+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
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+ u32 serdes2_prtcl;
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+ int ret = 0;
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+ int i;
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+
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+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
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+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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+ if (!serdes2_prtcl) {
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+ debug("SERDES2 is not enabled\n");
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+ return -ENODEV;
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+ }
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+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
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+
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+ /* To prevent generation of reset request from SerDes
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+ * while changing the refclks, By setting SRDS_RST_MSK bit,
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+ * SerDes reset event cannot cause a reset request
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+ */
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+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
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+
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+ /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
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+ * For this SerDes2's Refclk1 need to be set to 100MHz
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+ */
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+ switch (serdes2_prtcl) {
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+ case 0x9E:
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+ case 0x9A:
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+ case 0xb2:
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+ debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
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+ serdes2_prtcl);
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+ ret = select_i2c_ch_pca(I2C_CH_IDT);
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+ if (!ret) {
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+ ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
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+ SERDES_REFCLK_100,
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+ SERDES_REFCLK_100, 0);
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+ if (ret) {
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+ printf("IDT8T49N222A configuration failed.\n");
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+ goto out;
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+ } else
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+ debug("IDT8T49N222A configured.\n");
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+ } else {
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+ goto out;
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+ }
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+ select_i2c_ch_pca(I2C_CH_DEFAULT);
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+
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+ /* Steps For SerDes PLLs reset and reconfiguration after
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+ * changing SerDes's refclks
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+ */
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+ for (i = 0; i < PLL_NUM; i++) {
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+ clrbits_be32(&srds2_regs->bank[i].rstctl,
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+ SRDS_RSTCTL_SDRST_B);
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+ udelay(10);
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+ clrbits_be32(&srds2_regs->bank[i].rstctl,
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+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
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+ udelay(10);
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+ setbits_be32(&srds2_regs->bank[i].rstctl,
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+ SRDS_RSTCTL_RST);
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+ setbits_be32(&srds2_regs->bank[i].rstctl,
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+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
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+ | SRDS_RSTCTL_SDRST_B));
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+ }
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+ break;
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+ default:
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+ printf("IDT configuration not supported for:%x S2 Protocol.\n",
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+ serdes2_prtcl);
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+ }
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+
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+out:
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+ /* Clearing SRDS_RST_MSK bit as now
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+ * SerDes reset event can cause a reset request
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+ */
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+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
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+ return ret;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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+ int ret;
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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@@ -442,6 +529,20 @@ int board_early_init_r(void)
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else
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printf("SerDes1 Refclks have been set.\n");
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+ /* SerDes2 refclks need to be set again, as default clks
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+ * are not suitable for PCIe SATA to work
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+ * This function will set SerDes2's Refclk1 and refclk2
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+ * for SerDes2 protocols having PCIe in them
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+ * for PCIe SATA to work
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+ */
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+ ret = config_serdes2_refclks();
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+ if (!ret)
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+ printf("SerDes2 Refclks have been set.\n");
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+ else if (ret == -ENODEV)
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+ printf("SerDes disable, Refclks couldn't change.\n");
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+ else
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+ printf("SerDes2 Refclk reconfiguring failed.\n");
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+
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/* Configure VSC3316 and VSC3308 crossbar switches */
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if (configure_vsc3316_3308())
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printf("VSC:failed to configure VSC3316/3308.\n");
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