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net, phy, cpsw: fix gigabit register access

accessing a lan9303 switch with the cpsw driver results in wrong
speed detection, as the switch sets the BMSR_ERCAP in BMSR
register, and follow read of the MII_STAT1000 register fails, as
the switch does not support it. Current code did not check,
if a phy_read() fails ... fix this.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Heiko Schocher 11 years ago
parent
commit
f6d1f6e4a5
3 changed files with 13 additions and 9 deletions
  1. 7 7
      boards.cfg
  2. 1 1
      drivers/net/cpsw.c
  3. 5 1
      drivers/net/phy/phy.c

+ 7 - 7
boards.cfg

@@ -241,16 +241,16 @@ integratorcp_cm946es         arm         arm946es    integrator          armltd
 vexpress_ca15_tc2            arm         armv7       vexpress            armltd
 vexpress_ca5x2               arm         armv7       vexpress            armltd
 vexpress_ca9x4               arm         armv7       vexpress            armltd
-am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1
+am335x_evm                   arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NAND
 am335x_evm_nor               arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NOR
 am335x_evm_norboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT
 am335x_evm_spiboot           arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
-am335x_evm_uart1             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL2,CONS_INDEX=2
-am335x_evm_uart2             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL3,CONS_INDEX=3
-am335x_evm_uart3             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL4,CONS_INDEX=4
-am335x_evm_uart4             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL5,CONS_INDEX=5
-am335x_evm_uart5             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL6,CONS_INDEX=6
-am335x_evm_usbspl            arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
+am335x_evm_uart1             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL2,CONS_INDEX=1,NAND
+am335x_evm_uart2             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL3,CONS_INDEX=1,NAND
+am335x_evm_uart3             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL4,CONS_INDEX=1,NAND
+am335x_evm_uart4             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL5,CONS_INDEX=1,NAND
+am335x_evm_uart5             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL6,CONS_INDEX=1,NAND
+am335x_evm_usbspl            arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT
 ti814x_evm                   arm         armv7       ti814x              ti             am33xx
 pcm051                       arm         armv7       pcm051              phytec         am33xx      pcm051
 sama5d3xek_mmc               arm         armv7       sama5d3xek          atmel          at91        sama5d3xek:SAMA5D3,SYS_USE_MMC

+ 1 - 1
drivers/net/cpsw.c

@@ -487,7 +487,7 @@ static inline void wait_for_idle(void)
 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
 				int dev_addr, int phy_reg)
 {
-	unsigned short data;
+	int data;
 	u32 reg;
 
 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)

+ 5 - 1
drivers/net/phy/phy.c

@@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev)
 	/* We're using autonegotiation */
 	if (mii_reg & BMSR_ANEGCAPABLE) {
 		u32 lpa = 0;
-		u32 gblpa = 0;
+		int gblpa = 0;
 		u32 estatus = 0;
 
 		/* Check for gigabit capability */
@@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev)
 			 * both PHYs in the link
 			 */
 			gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
+			if (gblpa < 0) {
+				debug("Could not read MII_STAT1000. Ignoring gigabit capability\n");
+				gblpa = 0;
+			}
 			gblpa &= phy_read(phydev,
 					MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
 		}