net: macb: Flush correct cache portion when sending

The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>

drivers/net/macb.c

@@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
 	barrier();
 	macb_flush_ring_desc(macb, TX);
 	/* Do we need check paddr and length is dcache line aligned? */
-	flush_dcache_range(paddr, paddr + length);
+	flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
 
 	/*