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@@ -0,0 +1,690 @@
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+/*
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+ * ***************************************************************************
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+ * Copyright (C) 2015 Marvell International Ltd.
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+ * ***************************************************************************
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+ * This program is free software: you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the Free
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+ * Software Foundation, either version 2 of the License, or any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ * ***************************************************************************
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+ */
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+/* pcie_advk.c
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+ *
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+ * Ported from Linux driver - driver/pci/host/pci-aardvark.c
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+ *
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+ * Author: Victor Gu <xigu@marvell.com>
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+ * Hezi Shahmoon <hezi.shahmoon@marvell.com>
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+ *
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+ */
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+
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+#include <common.h>
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+#include <dm.h>
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+#include <pci.h>
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+#include <asm/io.h>
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+#include <asm-generic/gpio.h>
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+#include <linux/ioport.h>
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+
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+/* PCIe core registers */
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+#define PCIE_CORE_CMD_STATUS_REG 0x4
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+#define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
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+#define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
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+#define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
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+#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
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+#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
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+#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
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+#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
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+#define PCIE_CORE_LINK_TRAINING BIT(5)
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+#define PCIE_CORE_ERR_CAPCTL_REG 0x118
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+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
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+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
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+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
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+#define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
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+
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+/* PIO registers base address and register offsets */
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+#define PIO_BASE_ADDR 0x4000
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+#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
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+#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
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+#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
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+#define PIO_STAT (PIO_BASE_ADDR + 0x4)
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+#define PIO_COMPLETION_STATUS_SHIFT 7
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+#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
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+#define PIO_COMPLETION_STATUS_OK 0
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+#define PIO_COMPLETION_STATUS_UR 1
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+#define PIO_COMPLETION_STATUS_CRS 2
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+#define PIO_COMPLETION_STATUS_CA 4
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+#define PIO_NON_POSTED_REQ BIT(10)
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+#define PIO_ERR_STATUS BIT(11)
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+#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
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+#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
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+#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
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+#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
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+#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
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+#define PIO_START (PIO_BASE_ADDR + 0x1c)
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+#define PIO_ISR (PIO_BASE_ADDR + 0x20)
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+
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+/* Aardvark Control registers */
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+#define CONTROL_BASE_ADDR 0x4800
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+#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
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+#define PCIE_GEN_SEL_MSK 0x3
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+#define PCIE_GEN_SEL_SHIFT 0x0
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+#define SPEED_GEN_1 0
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+#define SPEED_GEN_2 1
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+#define SPEED_GEN_3 2
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+#define IS_RC_MSK 1
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+#define IS_RC_SHIFT 2
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+#define LANE_CNT_MSK 0x18
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+#define LANE_CNT_SHIFT 0x3
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+#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
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+#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
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+#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
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+#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
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+#define LINK_TRAINING_EN BIT(6)
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+#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
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+#define PCIE_CORE_CTRL2_RESERVED 0x7
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+#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
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+#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
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+#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
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+
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+/* LMI registers base address and register offsets */
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+#define LMI_BASE_ADDR 0x6000
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+#define CFG_REG (LMI_BASE_ADDR + 0x0)
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+#define LTSSM_SHIFT 24
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+#define LTSSM_MASK 0x3f
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+#define LTSSM_L0 0x10
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+
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+/* PCIe core controller registers */
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+#define CTRL_CORE_BASE_ADDR 0x18000
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+#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
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+#define CTRL_MODE_SHIFT 0x0
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+#define CTRL_MODE_MASK 0x1
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+#define PCIE_CORE_MODE_DIRECT 0x0
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+#define PCIE_CORE_MODE_COMMAND 0x1
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+
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+/* Transaction types */
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+#define PCIE_CONFIG_RD_TYPE0 0x8
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+#define PCIE_CONFIG_RD_TYPE1 0x9
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+#define PCIE_CONFIG_WR_TYPE0 0xa
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+#define PCIE_CONFIG_WR_TYPE1 0xb
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+
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+/* PCI_BDF shifts 8bit, so we need extra 4bit shift */
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+#define PCIE_BDF(dev) (dev << 4)
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+#define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
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+#define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
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+#define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
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+#define PCIE_CONF_REG(reg) ((reg) & 0xffc)
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+#define PCIE_CONF_ADDR(bus, devfn, where) \
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+ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
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+ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
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+
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+/* PCIe Retries & Timeout definitions */
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+#define MAX_RETRIES 10
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+#define PIO_WAIT_TIMEOUT 100
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+#define LINK_WAIT_TIMEOUT 100000
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+
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+#define CFG_RD_UR_VAL 0xFFFFFFFF
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+#define CFG_RD_CRS_VAL 0xFFFF0001
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+/**
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+ * struct pcie_advk - Advk PCIe controller state
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+ *
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+ * @reg_base: The base address of the register space.
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+ * @first_busno: This driver supports multiple PCIe controllers.
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+ * first_busno stores the bus number of the PCIe root-port
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+ * number which may vary depending on the PCIe setup
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+ * (PEX switches etc).
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+ * @device: The pointer to PCI uclass device.
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+ */
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+struct pcie_advk {
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+ void *base;
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+ int first_busno;
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+ struct udevice *dev;
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+};
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+
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+static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
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+{
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+ writel(val, pcie->base + reg);
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+}
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+
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+static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
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+{
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+ return readl(pcie->base + reg);
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+}
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+
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+/**
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+ * pcie_advk_addr_valid() - Check for valid bus address
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+ *
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+ * @bdf: The PCI device to access
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+ * @first_busno: Bus number of the PCIe controller root complex
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+ *
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+ * Return: 1 on valid, 0 on invalid
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+ */
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+static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
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+{
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+ /*
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+ * In PCIE-E only a single device (0) can exist
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+ * on the local bus. Beyound the local bus, there might be
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+ * a Switch and everything is possible.
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+ */
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+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
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+ return 0;
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+
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+ return 1;
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+}
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+
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+/**
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+ * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
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+ *
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+ * @pcie: The PCI device to access
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+ *
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+ * Wait up to 1 micro second for PIO access to be accomplished.
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+ *
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+ * Return 1 (true) if PIO access is accomplished.
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+ * Return 0 (false) if PIO access is timed out.
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+ */
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+static int pcie_advk_wait_pio(struct pcie_advk *pcie)
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+{
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+ uint start, isr;
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+ uint count;
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+
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+ for (count = 0; count < MAX_RETRIES; count++) {
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+ start = advk_readl(pcie, PIO_START);
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+ isr = advk_readl(pcie, PIO_ISR);
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+ if (!start && isr)
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+ return 1;
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+ /*
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+ * Do not check the PIO state too frequently,
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+ * 100us delay is appropriate.
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+ */
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+ udelay(PIO_WAIT_TIMEOUT);
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+ }
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+
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+ dev_err(pcie->dev, "config read/write timed out\n");
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+ return 0;
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+}
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+
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+/**
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+ * pcie_advk_check_pio_status() - Validate PIO status and get the read result
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+ *
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+ * @pcie: Pointer to the PCI bus
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+ * @read: Read from or write to configuration space - true(read) false(write)
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+ * @read_val: Pointer to the read result, only valid when read is true
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+ *
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+ */
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+static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
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+ bool read,
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+ uint *read_val)
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+{
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+ uint reg;
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+ unsigned int status;
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+ char *strcomp_status, *str_posted;
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+
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+ reg = advk_readl(pcie, PIO_STAT);
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+ status = (reg & PIO_COMPLETION_STATUS_MASK) >>
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+ PIO_COMPLETION_STATUS_SHIFT;
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+
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+ switch (status) {
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+ case PIO_COMPLETION_STATUS_OK:
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+ if (reg & PIO_ERR_STATUS) {
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+ strcomp_status = "COMP_ERR";
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+ break;
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+ }
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+ /* Get the read result */
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+ if (read)
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+ *read_val = advk_readl(pcie, PIO_RD_DATA);
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+ /* No error */
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+ strcomp_status = NULL;
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+ break;
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+ case PIO_COMPLETION_STATUS_UR:
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+ if (read) {
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+ /* For reading, UR is not an error status. */
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+ *read_val = CFG_RD_UR_VAL;
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+ strcomp_status = NULL;
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+ } else {
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+ strcomp_status = "UR";
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+ }
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+ break;
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+ case PIO_COMPLETION_STATUS_CRS:
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+ if (read) {
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+ /* For reading, CRS is not an error status. */
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+ *read_val = CFG_RD_CRS_VAL;
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+ strcomp_status = NULL;
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+ } else {
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+ strcomp_status = "CRS";
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+ }
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+ break;
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+ case PIO_COMPLETION_STATUS_CA:
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+ strcomp_status = "CA";
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+ break;
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+ default:
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+ strcomp_status = "Unknown";
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+ break;
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+ }
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+
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+ if (!strcomp_status)
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+ return 0;
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+
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+ if (reg & PIO_NON_POSTED_REQ)
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+ str_posted = "Non-posted";
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+ else
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+ str_posted = "Posted";
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+
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+ dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
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+ str_posted, strcomp_status, reg,
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+ advk_readl(pcie, PIO_ADDR_LS));
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+
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+ return -EFAULT;
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+}
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+
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+/**
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+ * pcie_advk_read_config() - Read from configuration space
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+ *
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+ * @bus: Pointer to the PCI bus
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+ * @bdf: Identifies the PCIe device to access
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+ * @offset: The offset into the device's configuration space
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+ * @valuep: A pointer at which to store the read value
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+ * @size: Indicates the size of access to perform
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+ *
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+ * Read a value of size @size from offset @offset within the configuration
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+ * space of the device identified by the bus, device & function numbers in @bdf
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+ * on the PCI bus @bus.
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+ *
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+ * Return: 0 on success
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+ */
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+static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
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+ uint offset, ulong *valuep,
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+ enum pci_size_t size)
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+{
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+ struct pcie_advk *pcie = dev_get_priv(bus);
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+ uint reg;
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+ int ret;
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+
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+ dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
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+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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+
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+ if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
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+ dev_dbg(pcie->dev, "- out of range\n");
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+ *valuep = pci_get_ff(size);
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+ return 0;
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+ }
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+
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+ /* Start PIO */
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+ advk_writel(pcie, 0, PIO_START);
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+ advk_writel(pcie, 1, PIO_ISR);
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+
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+ /* Program the control register */
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+ reg = advk_readl(pcie, PIO_CTRL);
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+ reg &= ~PIO_CTRL_TYPE_MASK;
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+ if (PCI_BUS(bdf) == pcie->first_busno)
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+ reg |= PCIE_CONFIG_RD_TYPE0;
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+ else
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+ reg |= PCIE_CONFIG_RD_TYPE1;
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+ advk_writel(pcie, reg, PIO_CTRL);
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+
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+ /* Program the address registers */
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+ reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
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+ advk_writel(pcie, reg, PIO_ADDR_LS);
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+ advk_writel(pcie, 0, PIO_ADDR_MS);
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+
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+ /* Start the transfer */
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+ advk_writel(pcie, 1, PIO_START);
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+
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+ if (!pcie_advk_wait_pio(pcie))
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+ return -EINVAL;
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+
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+ /* Check PIO status and get the read result */
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+ ret = pcie_advk_check_pio_status(pcie, true, ®);
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+ if (ret)
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+ return ret;
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+
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+ dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
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+ offset, size, reg);
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+ *valuep = pci_conv_32_to_size(reg, offset, size);
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+
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+ return 0;
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+}
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+
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+/**
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+ * pcie_calc_datastrobe() - Calculate data strobe
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+ *
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+ * @offset: The offset into the device's configuration space
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+ * @size: Indicates the size of access to perform
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+ *
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+ * Calculate data strobe according to offset and size
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+ *
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+ */
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+static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
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+{
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+ uint bytes, data_strobe;
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+
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+ switch (size) {
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+ case PCI_SIZE_8:
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+ bytes = 1;
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+ break;
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+ case PCI_SIZE_16:
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+ bytes = 2;
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+ break;
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+ default:
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+ bytes = 4;
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+ }
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+
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+ data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
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+
|
|
|
+ return data_strobe;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_write_config() - Write to configuration space
|
|
|
+ *
|
|
|
+ * @bus: Pointer to the PCI bus
|
|
|
+ * @bdf: Identifies the PCIe device to access
|
|
|
+ * @offset: The offset into the device's configuration space
|
|
|
+ * @value: The value to write
|
|
|
+ * @size: Indicates the size of access to perform
|
|
|
+ *
|
|
|
+ * Write the value @value of size @size from offset @offset within the
|
|
|
+ * configuration space of the device identified by the bus, device & function
|
|
|
+ * numbers in @bdf on the PCI bus @bus.
|
|
|
+ *
|
|
|
+ * Return: 0 on success
|
|
|
+ */
|
|
|
+static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
|
|
|
+ uint offset, ulong value,
|
|
|
+ enum pci_size_t size)
|
|
|
+{
|
|
|
+ struct pcie_advk *pcie = dev_get_priv(bus);
|
|
|
+ uint reg;
|
|
|
+
|
|
|
+ dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
|
|
|
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
|
|
|
+ dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
|
|
|
+ offset, size, value);
|
|
|
+
|
|
|
+ if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
|
|
|
+ dev_dbg(pcie->dev, "- out of range\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Start PIO */
|
|
|
+ advk_writel(pcie, 0, PIO_START);
|
|
|
+ advk_writel(pcie, 1, PIO_ISR);
|
|
|
+
|
|
|
+ /* Program the control register */
|
|
|
+ reg = advk_readl(pcie, PIO_CTRL);
|
|
|
+ reg &= ~PIO_CTRL_TYPE_MASK;
|
|
|
+ if (PCI_BUS(bdf) == pcie->first_busno)
|
|
|
+ reg |= PCIE_CONFIG_WR_TYPE0;
|
|
|
+ else
|
|
|
+ reg |= PCIE_CONFIG_WR_TYPE1;
|
|
|
+ advk_writel(pcie, reg, PIO_CTRL);
|
|
|
+
|
|
|
+ /* Program the address registers */
|
|
|
+ reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
|
|
|
+ advk_writel(pcie, reg, PIO_ADDR_LS);
|
|
|
+ advk_writel(pcie, 0, PIO_ADDR_MS);
|
|
|
+ dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
|
|
|
+
|
|
|
+ /* Program the data register */
|
|
|
+ reg = pci_conv_size_to_32(0, value, offset, size);
|
|
|
+ advk_writel(pcie, reg, PIO_WR_DATA);
|
|
|
+ dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
|
|
|
+
|
|
|
+ /* Program the data strobe */
|
|
|
+ reg = pcie_calc_datastrobe(offset, size);
|
|
|
+ advk_writel(pcie, reg, PIO_WR_DATA_STRB);
|
|
|
+ dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
|
|
|
+
|
|
|
+ /* Start the transfer */
|
|
|
+ advk_writel(pcie, 1, PIO_START);
|
|
|
+
|
|
|
+ if (!pcie_advk_wait_pio(pcie)) {
|
|
|
+ dev_dbg(pcie->dev, "- wait pio timeout\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check PIO status */
|
|
|
+ pcie_advk_check_pio_status(pcie, false, ®);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_link_up() - Check if PCIe link is up or not
|
|
|
+ *
|
|
|
+ * @pcie: The PCI device to access
|
|
|
+ *
|
|
|
+ * Return 1 (true) on link up.
|
|
|
+ * Return 0 (false) on link down.
|
|
|
+ */
|
|
|
+static int pcie_advk_link_up(struct pcie_advk *pcie)
|
|
|
+{
|
|
|
+ u32 val, ltssm_state;
|
|
|
+
|
|
|
+ val = advk_readl(pcie, CFG_REG);
|
|
|
+ ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
|
|
|
+ return ltssm_state >= LTSSM_L0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_wait_for_link() - Wait for link training to be accomplished
|
|
|
+ *
|
|
|
+ * @pcie: The PCI device to access
|
|
|
+ *
|
|
|
+ * Wait up to 1 second for link training to be accomplished.
|
|
|
+ *
|
|
|
+ * Return 1 (true) if link training ends up with link up success.
|
|
|
+ * Return 0 (false) if link training ends up with link up failure.
|
|
|
+ */
|
|
|
+static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
|
|
|
+{
|
|
|
+ int retries;
|
|
|
+
|
|
|
+ /* check if the link is up or not */
|
|
|
+ for (retries = 0; retries < MAX_RETRIES; retries++) {
|
|
|
+ if (pcie_advk_link_up(pcie)) {
|
|
|
+ printf("PCIE-%d: Link up\n", pcie->first_busno);
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ udelay(LINK_WAIT_TIMEOUT);
|
|
|
+ }
|
|
|
+
|
|
|
+ printf("PCIE-%d: Link down\n", pcie->first_busno);
|
|
|
+
|
|
|
+ return -ETIMEDOUT;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_setup_hw() - PCIe initailzation
|
|
|
+ *
|
|
|
+ * @pcie: The PCI device to access
|
|
|
+ *
|
|
|
+ * Return: 0 on success
|
|
|
+ */
|
|
|
+static int pcie_advk_setup_hw(struct pcie_advk *pcie)
|
|
|
+{
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ /* Set to Direct mode */
|
|
|
+ reg = advk_readl(pcie, CTRL_CONFIG_REG);
|
|
|
+ reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
|
|
|
+ reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
|
|
|
+ advk_writel(pcie, reg, CTRL_CONFIG_REG);
|
|
|
+
|
|
|
+ /* Set PCI global control register to RC mode */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
+ reg |= (IS_RC_MSK << IS_RC_SHIFT);
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
+
|
|
|
+ /* Set Advanced Error Capabilities and Control PF0 register */
|
|
|
+ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
|
|
|
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
|
|
|
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
|
|
|
+ PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
|
|
|
+
|
|
|
+ /* Set PCIe Device Control and Status 1 PF0 register */
|
|
|
+ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
|
|
|
+ PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
|
|
+
|
|
|
+ /* Program PCIe Control 2 to disable strict ordering */
|
|
|
+ reg = PCIE_CORE_CTRL2_RESERVED |
|
|
|
+ PCIE_CORE_CTRL2_TD_ENABLE;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
+
|
|
|
+ /* Set GEN2 */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
+ reg &= ~PCIE_GEN_SEL_MSK;
|
|
|
+ reg |= SPEED_GEN_2;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
+
|
|
|
+ /* Set lane X1 */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
+ reg &= ~LANE_CNT_MSK;
|
|
|
+ reg |= LANE_COUNT_1;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
+
|
|
|
+ /* Enable link training */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
+ reg |= LINK_TRAINING_EN;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Enable AXI address window location generation:
|
|
|
+ * When it is enabled, the default outbound window
|
|
|
+ * configurations (Default User Field: 0xD0074CFC)
|
|
|
+ * are used to transparent address translation for
|
|
|
+ * the outbound transactions. Thus, PCIe address
|
|
|
+ * windows are not required.
|
|
|
+ */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
|
|
|
+ reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Bypass the address window mapping for PIO:
|
|
|
+ * Since PIO access already contains all required
|
|
|
+ * info over AXI interface by PIO registers, the
|
|
|
+ * address window is not required.
|
|
|
+ */
|
|
|
+ reg = advk_readl(pcie, PIO_CTRL);
|
|
|
+ reg |= PIO_CTRL_ADDR_WIN_DISABLE;
|
|
|
+ advk_writel(pcie, reg, PIO_CTRL);
|
|
|
+
|
|
|
+ /* Start link training */
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
|
|
|
+ reg |= PCIE_CORE_LINK_TRAINING;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
|
|
|
+
|
|
|
+ /* Wait for PCIe link up */
|
|
|
+ if (pcie_advk_wait_for_link(pcie))
|
|
|
+ return -ENXIO;
|
|
|
+
|
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
|
|
+ reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
|
|
|
+ PCIE_CORE_CMD_IO_ACCESS_EN |
|
|
|
+ PCIE_CORE_CMD_MEM_IO_REQ_EN;
|
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_probe() - Probe the PCIe bus for active link
|
|
|
+ *
|
|
|
+ * @dev: A pointer to the device being operated on
|
|
|
+ *
|
|
|
+ * Probe for an active link on the PCIe bus and configure the controller
|
|
|
+ * to enable this port.
|
|
|
+ *
|
|
|
+ * Return: 0 on success, else -ENODEV
|
|
|
+ */
|
|
|
+static int pcie_advk_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct pcie_advk *pcie = dev_get_priv(dev);
|
|
|
+
|
|
|
+#ifdef CONFIG_DM_GPIO
|
|
|
+ struct gpio_desc reset_gpio;
|
|
|
+
|
|
|
+ gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
|
|
|
+ GPIOD_IS_OUT);
|
|
|
+ /*
|
|
|
+ * Issue reset to add-in card through the dedicated GPIO.
|
|
|
+ * Some boards are connecting the card reset pin to common system
|
|
|
+ * reset wire and others are using separate GPIO port.
|
|
|
+ * In the last case we have to release a reset of the addon card
|
|
|
+ * using this GPIO.
|
|
|
+ *
|
|
|
+ * FIX-ME:
|
|
|
+ * The PCIe RESET signal is not supposed to be released along
|
|
|
+ * with the SOC RESET signal. It should be lowered as early as
|
|
|
+ * possible before PCIe PHY initialization. Moreover, the PCIe
|
|
|
+ * clock should be gated as well.
|
|
|
+ */
|
|
|
+ if (dm_gpio_is_valid(&reset_gpio)) {
|
|
|
+ dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
|
|
|
+ dm_gpio_set_value(&reset_gpio, 0);
|
|
|
+ mdelay(200);
|
|
|
+ dm_gpio_set_value(&reset_gpio, 1);
|
|
|
+ }
|
|
|
+#else
|
|
|
+ dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
|
|
|
+#endif /* CONFIG_DM_GPIO */
|
|
|
+
|
|
|
+ pcie->first_busno = dev->seq;
|
|
|
+ pcie->dev = pci_get_controller(dev);
|
|
|
+
|
|
|
+ return pcie_advk_setup_hw(pcie);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
|
|
|
+ *
|
|
|
+ * @dev: A pointer to the device being operated on
|
|
|
+ *
|
|
|
+ * Translate relevant data from the device tree pertaining to device @dev into
|
|
|
+ * state that the driver will later make use of. This state is stored in the
|
|
|
+ * device's private data structure.
|
|
|
+ *
|
|
|
+ * Return: 0 on success, else -EINVAL
|
|
|
+ */
|
|
|
+static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct pcie_advk *pcie = dev_get_priv(dev);
|
|
|
+
|
|
|
+ /* Get the register base address */
|
|
|
+ pcie->base = (void *)dev_read_addr_index(dev, 0);
|
|
|
+ if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct dm_pci_ops pcie_advk_ops = {
|
|
|
+ .read_config = pcie_advk_read_config,
|
|
|
+ .write_config = pcie_advk_write_config,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct udevice_id pcie_advk_ids[] = {
|
|
|
+ { .compatible = "marvell,armada-37xx-pcie" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(pcie_advk) = {
|
|
|
+ .name = "pcie_advk",
|
|
|
+ .id = UCLASS_PCI,
|
|
|
+ .of_match = pcie_advk_ids,
|
|
|
+ .ops = &pcie_advk_ops,
|
|
|
+ .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
|
|
|
+ .probe = pcie_advk_probe,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct pcie_advk),
|
|
|
+};
|
Tom Rini