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@@ -52,8 +52,8 @@
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR 0xFFFFFF64
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#define EBI_CFGR_VAL 0x00000000
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-#define SMC2_CSR 0xFFFFFF70
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-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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+#define SMC_CSR0 0xFFFFFF70
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+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define PLLAR 0xFFFFFC28
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@@ -141,8 +141,8 @@ SMRDATA:
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.word MC_AASR_VAL
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.word EBI_CFGR
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.word EBI_CFGR_VAL
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- .word SMC2_CSR
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- .word SMC2_CSR_VAL
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+ .word SMC_CSR0
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+ .word SMC_CSR0_VAL
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.word PLLAR
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.word PLLAR_VAL
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.word PLLBR
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