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@@ -200,9 +200,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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case CLK_TYPE_GEN3_PLL1:
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rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
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- debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%llu\n",
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+ rate /= pll_config->pll1_div;
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+ debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
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__func__, __LINE__,
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- core->parent, pll_config->pll1_mult, rate);
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+ core->parent, pll_config->pll1_mult,
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+ pll_config->pll1_div, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL2:
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@@ -215,9 +217,11 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
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case CLK_TYPE_GEN3_PLL3:
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rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
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- debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%llu\n",
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+ rate /= pll_config->pll3_div;
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+ debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
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__func__, __LINE__,
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- core->parent, pll_config->pll3_mult, rate);
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+ core->parent, pll_config->pll3_mult,
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+ pll_config->pll3_div, rate);
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return rate;
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case CLK_TYPE_GEN3_PLL4:
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