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@@ -838,6 +838,31 @@ static int config_ddr_clk(u32 emi_clk)
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return 0;
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}
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+#ifdef CONFIG_MX53
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+static int config_ldb_clk(u32 ref, u32 freq)
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+{
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+ int ret = 0;
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+ struct pll_param pll_param;
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+
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+ memset(&pll_param, 0, sizeof(struct pll_param));
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+
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+ ret = calc_pll_params(ref, freq, &pll_param);
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+ if (ret != 0) {
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+ printf("Error:Can't find pll parameters: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ return config_pll_clk(PLL4_CLOCK, &pll_param);
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+}
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+#else
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+static int config_ldb_clk(u32 ref, u32 freq)
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+{
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+ /* Platform not supported */
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+ return -EINVAL;
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+}
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+#endif
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+
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/*
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* This function assumes the expected core clock has to be changed by
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* modifying the PLL. This is NOT true always but for most of the times,
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@@ -879,6 +904,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
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if (config_nfc_clk(freq))
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return -EINVAL;
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break;
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+ case MXC_LDB_CLK:
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+ if (config_ldb_clk(ref, freq))
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+ return -EINVAL;
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+ break;
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default:
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printf("Warning:Unsupported or invalid clock type\n");
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}
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