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@@ -28,6 +28,7 @@
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#include <asm/arch/tegra2.h>
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#include <common.h>
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#include <div64.h>
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+#include <fdtdec.h>
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/*
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* This is our record of the current clock rate of each clock. We don't
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@@ -918,6 +919,63 @@ void clock_ll_start_uart(enum periph_id periph_id)
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reset_set_enable(periph_id, 0);
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}
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+#ifdef CONFIG_OF_CONTROL
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+/*
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+ * Convert a device tree clock ID to our peripheral ID. They are mostly
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+ * the same but we are very cautious so we check that a valid clock ID is
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+ * provided.
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+ *
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+ * @param clk_id Clock ID according to tegra2 device tree binding
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+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
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+ */
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+static enum periph_id clk_id_to_periph_id(int clk_id)
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+{
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+ if (clk_id > 95)
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+ return PERIPH_ID_NONE;
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+
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+ switch (clk_id) {
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+ case 1:
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+ case 2:
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+ case 7:
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+ case 10:
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+ case 20:
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+ case 30:
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+ case 35:
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+ case 49:
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+ case 56:
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+ case 74:
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+ case 76:
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+ case 77:
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+ case 78:
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+ case 79:
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+ case 80:
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+ case 81:
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+ case 82:
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+ case 83:
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+ case 91:
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+ case 95:
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+ return PERIPH_ID_NONE;
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+ default:
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+ return clk_id;
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+ }
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+}
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+
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+int clock_decode_periph_id(const void *blob, int node)
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+{
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+ enum periph_id id;
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+ u32 cell[2];
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+ int err;
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+
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+ err = fdtdec_get_int_array(blob, node, "clocks", cell,
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+ ARRAY_SIZE(cell));
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+ if (err)
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+ return -1;
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+ id = clk_id_to_periph_id(cell[1]);
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+ assert(clock_periph_id_isvalid(id));
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+ return id;
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+}
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+#endif /* CONFIG_OF_CONTROL */
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+
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int clock_verify(void)
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{
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struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
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