Merge branch 'u-boot/master' into 'u-boot-arm/master'

.gitignore

@@ -20,7 +20,9 @@
 *.bin
 *.patch
 *.cfgtmp
-*.dts.tmp
+
+# host programs on Cygwin
+*.exe
 
 # Build tree
 /build-*
@@ -47,8 +49,7 @@
 /errlog
 /reloc_off
 
-/spl/*
-!/spl/Makefile
+/spl/
 /tpl/
 
 #

Makefile

@@ -8,7 +8,7 @@
 VERSION = 2014
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -209,11 +209,6 @@ HOSTCXX      = g++
 HOSTCFLAGS   = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
 HOSTCXXFLAGS = -O2
 
-ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
-HOSTCFLAGS  += -Wno-unused-value -Wno-unused-parameter \
-		-Wno-missing-field-initializers -fno-delete-null-pointer-checks
-endif
-
 ifeq ($(HOSTOS),cygwin)
 HOSTCFLAGS	+= -ansi
 endif
@@ -249,18 +244,18 @@ endif
 KBUILD_MODULES :=
 KBUILD_BUILTIN := 1
 
-#	If we have only "make modules", don't compile built-in objects.
-#	When we're building modules with modversions, we need to consider
-#	the built-in objects during the descend as well, in order to
-#	make sure the checksums are up to date before we record them.
+# If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
 
 ifeq ($(MAKECMDGOALS),modules)
   KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
 endif
 
-#	If we have "make <whatever> modules", compile modules
-#	in addition to whatever we do anyway.
-#	Just "make" or "make all" shall build modules as well
+# If we have "make <whatever> modules", compile modules
+# in addition to whatever we do anyway.
+# Just "make" or "make all" shall build modules as well
 
 # U-Boot does not need modules
 #ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
@@ -320,15 +315,6 @@ endif
 
 export quiet Q KBUILD_VERBOSE
 
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
 # Look for make include files relative to root of kernel src
 MAKEFLAGS += --include-dir=$(srctree)
 
@@ -354,7 +340,7 @@ STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
 AWK		= awk
-RANLIB		= $(CROSS_COMPILE)RANLIB
+PERL		= perl
 DTC		= dtc
 CHECK		= sparse
 
@@ -376,8 +362,8 @@ export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
 export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
 export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
 export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK
-export DTC CHECK CHECKFLAGS
+export MAKE AWK PERL
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
 
 export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
 export KBUILD_CFLAGS KBUILD_AFLAGS
@@ -515,12 +501,6 @@ endif
 
 # If there is no specified link script, we look in a number of places for it
 ifndef LDSCRIPT
-	ifeq ($(CONFIG_NAND_U_BOOT),y)
-		LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
-		ifeq ($(wildcard $(LDSCRIPT)),)
-			LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
-		endif
-	endif
 	ifeq ($(wildcard $(LDSCRIPT)),)
 		LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
 	endif
@@ -545,20 +525,6 @@ endif
 
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 
-ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
-KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
-KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
-KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
-KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-# Quiet clang warning: comparison of unsigned expression < 0 is always false
-KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
-# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
-# source of a reference will be _MergedGlobals and not on of the whitelisted names.
-# See modpost pattern 2
-KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
-endif
-
 KBUILD_CFLAGS	+= -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
@@ -740,9 +706,8 @@ DO_STATIC_RELA =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin System.map
+ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
 
-ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
 ifeq ($(CONFIG_SPL_FSL_PBL),y)
 ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
@@ -820,6 +785,18 @@ u-boot.hex u-boot.srec: u-boot FORCE
 
 OBJCOPYFLAGS_u-boot.bin := -O binary
 
+binary_size_check: u-boot.bin System.map FORCE
+	@file_size=`stat -c %s u-boot.bin` ; \
+	map_size=$(shell cat System.map | \
+		awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+	if [ "" != "$$map_size" ]; then \
+		if test $$map_size -ne $$file_size; then \
+			echo "System.map shows a binary size of $$map_size" >&2 ; \
+			echo "  but u-boot.bin shows $$file_size" >&2 ; \
+			exit 1; \
+		fi \
+	fi
+
 u-boot.bin: u-boot FORCE
 	$(call if_changed,objcopy)
 	$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
@@ -1148,33 +1125,16 @@ cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
 u-boot.lds: $(LDSCRIPT) prepare FORCE
 	$(call if_changed_dep,cpp_lds)
 
-PHONY += nand_spl
-nand_spl: prepare
-	$(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
-	@echo >&2
-	@echo >&2 "==================== WARNING ====================="
-	@echo >&2 "nand_spl will not be included in v2014.07 release."
-	@echo >&2 "Please switch over to SPL."
-	@echo >&2 "Otherwise, this board will be removed."
-	@echo >&2 "=================================================="
-	@echo >&2
-
-nand_spl/u-boot-spl-16k.bin: nand_spl
-	@:
-
-u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
-	$(call if_changed,cat)
-
 spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
 spl/u-boot-spl: tools prepare
-	$(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+	$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
 	@:
 
 tpl/u-boot-tpl.bin: tools prepare
-	$(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+	$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
 
 TAG_SUBDIRS := $(u-boot-dirs) include
 
@@ -1254,14 +1214,12 @@ CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h \
 	       include/tpl-autoconf.mk
 
 # Directories & files removed with 'make clobber'
-CLOBBER_DIRS  += $(patsubst %,spl/%, $(filter-out Makefile, \
-		 $(shell ls -1 spl 2>/dev/null))) \
-		 tpl
-CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+CLOBBER_DIRS  += spl tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated          \
-                  .tmp_objdiff
+		  .tmp_objdiff
 MRPROPER_FILES += .config .config.old \
 		  tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
 		  include/config.h include/config.mk
@@ -1290,8 +1248,6 @@ clean: $(clean-dirs)
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
-	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
-		-path './nand_spl/*' -type l -print | xargs rm -f
 
 # clobber
 #

README

@@ -321,14 +321,6 @@ The following options need to be configured:
 					  the LCD display every second with
 					  a "rotator" |\-/|\-/
 
-- Board flavour: (if CONFIG_MPC8260ADS is defined)
-		CONFIG_ADSTYPE
-		Possible values are:
-			CONFIG_SYS_8260ADS	- original MPC8260ADS
-			CONFIG_SYS_8266ADS	- MPC8266ADS
-			CONFIG_SYS_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR
-			CONFIG_SYS_8272ADS	- MPC8272ADS
-
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -1008,6 +1000,7 @@ The following options need to be configured:
 		CONFIG_CMD_IMLS		  List all images found in NOR flash
 		CONFIG_CMD_IMLS_NAND	* List all images found in NAND flash
 		CONFIG_CMD_IMMAP	* IMMR dump support
+		CONFIG_CMD_IOTRACE	* I/O tracing for debugging
 		CONFIG_CMD_IMPORTENV	* import an environment
 		CONFIG_CMD_INI		* import data from an ini file into the env
 		CONFIG_CMD_IRQ		* irqinfo
@@ -1179,6 +1172,28 @@ The following options need to be configured:
 		Note that if the GPIO device uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 
+- I/O tracing:
+		When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
+		accesses and can checksum them or write a list of them out
+		to memory. See the 'iotrace' command for details. This is
+		useful for testing device drivers since it can confirm that
+		the driver behaves the same way before and after a code
+		change. Currently this is supported on sandbox and arm. To
+		add support for your architecture, add '#include <iotrace.h>'
+		to the bottom of arch/<arch>/include/asm/io.h and test.
+
+		Example output from the 'iotrace stats' command is below.
+		Note that if the trace buffer is exhausted, the checksum will
+		still continue to operate.
+
+			iotrace is enabled
+			Start:  10000000	(buffer start address)
+			Size:   00010000	(buffer size)
+			Offset: 00000120	(current buffer offset)
+			Output: 10000120	(start + offset)
+			Count:  00000018	(number of trace records)
+			CRC32:  9526fb66	(CRC32 of all trace records)
+
 - Timestamp Support:
 
 		When CONFIG_TIMESTAMP is selected, the timestamp
@@ -1432,9 +1447,6 @@ The following options need to be configured:
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
 
-		CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
-		interval for usb hub power-on delay.(minimum 100msec)
-
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the
@@ -1645,6 +1657,12 @@ CBFS (Coreboot Filesystem) support
 		filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
 		and cbfsload.
 
+- FAT(File Allocation Table) filesystem cluster size:
+		CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+		Define the max cluster size for fat operations else
+		a default value of 65536 will be defined.
+
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD
 
@@ -3202,6 +3220,19 @@ FIT uImage format:
  -150	common/cmd_nand.c	Incorrect FIT image format
   151	common/cmd_nand.c	FIT image format OK
 
+- legacy image format:
+		CONFIG_IMAGE_FORMAT_LEGACY
+		enables the legacy image format support in U-Boot.
+
+		Default:
+		enabled if CONFIG_FIT_SIGNATURE is not defined.
+
+		CONFIG_DISABLE_IMAGE_LEGACY
+		disable the legacy image format
+
+		This define is introduced, as the legacy image format is
+		enabled per default for backward compatibility.
+
 - FIT image support:
 		CONFIG_FIT
 		Enable support for the FIT uImage format.
@@ -3218,6 +3249,11 @@ FIT uImage format:
 		using a hash signed and verified using RSA. See
 		doc/uImage.FIT/signature.txt for more details.
 
+		WARNING: When relying on signed FIT images with required
+		signature check the legacy image format is default
+		disabled. If a board need legacy image format support
+		enable this through CONFIG_IMAGE_FORMAT_LEGACY
+
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 
@@ -5295,6 +5331,11 @@ Information structure as we define in include/asm-<arch>/u-boot.h,
 and make sure that your definition of IMAP_ADDR uses the same value
 as your U-Boot configuration in CONFIG_SYS_IMMR.
 
+Note that U-Boot now has a driver model, a unified model for drivers.
+If you are adding a new driver, plumb it into driver model. If there
+is no uclass available, you are encouraged to create one. See
+doc/driver-model.
+
 
 Configuring the Linux kernel:
 -----------------------------

arch/.gitignore

@@ -1,2 +1 @@
 /*/include/asm/arch
-/*/include/asm/proc

arch/arc/include/asm/config.h

@@ -8,6 +8,7 @@
 #define __ASM_ARC_CONFIG_H_
 
 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
 
 #define CONFIG_LMB
 

arch/arm/cpu/arm926ejs/kirkwood/cpu.c

@@ -13,7 +13,6 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
-#include <hush.h>
 
 #define BUFLEN	16
 
@@ -211,7 +210,7 @@ static void kw_sysrst_action(void)
 
 	debug("Starting %s process...\n", __FUNCTION__);
 	ret = run_command(s, 0);
-	if (ret < 0)
+	if (ret != 0)
 		debug("Error.. %s failed\n", __FUNCTION__);
 	else
 		debug("%s process finished\n", __FUNCTION__);

arch/arm/cpu/arm926ejs/orion5x/cpu.c

@@ -15,7 +15,6 @@
 #include <asm/io.h>
 #include <u-boot/md5.h>
 #include <asm/arch/cpu.h>
-#include <hush.h>
 
 #define BUFLEN	16
 

arch/arm/cpu/armv7/am33xx/board.c

@@ -255,11 +255,3 @@ void s_init(void)
 #endif
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */

arch/arm/cpu/armv7/exynos/spl_boot.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include<common.h>
-#include<config.h>
+#include <common.h>
+#include <config.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>

arch/arm/cpu/armv7/omap-common/Makefile

@@ -22,6 +22,10 @@ obj-y	+= pipe3-phy.o
 obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
 endif
 
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y	+= omap-cache.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y	+= boot-common.o
 obj-y	+= lowlevel_init.o

arch/arm/cpu/armv7/omap-common/hwinit-common.c

@@ -18,13 +18,8 @@
 #include <asm/emif.h>
 #include <asm/omap_common.h>
 #include <linux/compiler.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
-#define ARMV7_DCACHE_WRITEBACK  0xe
-#define	ARMV7_DOMAIN_CLIENT	1
-#define ARMV7_DOMAIN_MASK	(0x3 << 0)
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
@@ -263,40 +258,3 @@ int print_cpuinfo(void)
 	return 0;
 }
 #endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
-	bd_t *bd = gd->bd;
-	int	i;
-
-	u32 start = bd->bi_dram[bank].start >> 20;
-	u32 size = bd->bi_dram[bank].size >> 20;
-	u32 end = start + size;
-
-	debug("%s: bank: %d\n", __func__, bank);
-	for (i = start; i < end; i++)
-		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
-	u32 reg;
-
-	reg = get_dacr();
-	/*
-	* Set DOMAIN to client access so that all permissions
-	* set in pagetables are validated by the mmu.
-	*/
-	reg &= ~ARMV7_DOMAIN_MASK;
-	reg |= ARMV7_DOMAIN_CLIENT;
-	set_dacr(reg);
-}
-#endif

arch/arm/cpu/armv7/omap-common/omap-cache.c

@@ -0,0 +1,56 @@
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *	Aneesh V	<aneesh@ti.com>
+ *	Steve Sakoman	<steve@sakoman.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARMV7_DCACHE_WRITEBACK  0xe
+#define ARMV7_DOMAIN_CLIENT	1
+#define ARMV7_DOMAIN_MASK	(0x3 << 0)
+
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+	bd_t *bd = gd->bd;
+	int	i;
+
+	u32 start = bd->bi_dram[bank].start >> 20;
+	u32 size = bd->bi_dram[bank].size >> 20;
+	u32 end = start + size;
+
+	debug("%s: bank: %d\n", __func__, bank);
+	for (i = start; i < end; i++)
+		set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+}
+
+void arm_init_domains(void)
+{
+	u32 reg;
+
+	reg = get_dacr();
+	/*
+	* Set DOMAIN to client access so that all permissions
+	* set in pagetables are validated by the mmu.
+	*/
+	reg &= ~ARMV7_DOMAIN_MASK;
+	reg |= ARMV7_DOMAIN_CLIENT;
+	set_dacr(reg);
+}

arch/arm/cpu/armv7/omap3/board.c

@@ -478,11 +478,3 @@ void omap3_outer_cache_disable(void)
 	omap3_update_aux_cr(0, 0x2);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */

arch/arm/dts/Makefile

@@ -31,6 +31,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 targets += $(dtb-y)
 

arch/arm/dts/am335x-bone-common.dtsi

@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	model = "TI AM335x BeagleBone";
+	compatible = "ti,am335x-bone", "ti,am33xx";
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&dcdc2_reg>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	am33xx_pinmux: pinmux@44e10800 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&clkout2_pin>;
+
+		user_leds_s0: user_leds_s0 {
+			pinctrl-single,pins = <
+				0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+				0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+				0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a7.gpio1_23 */
+				0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a8.gpio1_24 */
+			>;
+		};
+
+		i2c0_pins: pinmux_i2c0_pins {
+			pinctrl-single,pins = <
+				0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			>;
+		};
+
+		uart0_pins: pinmux_uart0_pins {
+			pinctrl-single,pins = <
+				0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+				0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+			>;
+		};
+
+		clkout2_pin: pinmux_clkout2_pin {
+			pinctrl-single,pins = <
+				0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+			>;
+		};
+
+		cpsw_default: cpsw_default {
+			pinctrl-single,pins = <
+				/* Slave 1 */
+				0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
+				0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
+				0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
+				0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
+				0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
+				0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
+				0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
+				0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
+				0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
+				0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
+				0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
+				0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
+				0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
+			>;
+		};
+
+		cpsw_sleep: cpsw_sleep {
+			pinctrl-single,pins = <
+				/* Slave 1 reset value */
+				0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+
+		davinci_mdio_default: davinci_mdio_default {
+			pinctrl-single,pins = <
+				/* MDIO */
+				0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+				0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			>;
+		};
+
+		davinci_mdio_sleep: davinci_mdio_sleep {
+			pinctrl-single,pins = <
+				/* MDIO reset value */
+				0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+				0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+	};
+
+	ocp {
+		uart0: serial@44e09000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins>;
+
+			status = "okay";
+		};
+
+		musb: usb@47400000 {
+			status = "okay";
+
+			control@44e10000 {
+				status = "okay";
+			};
+
+			usb-phy@47401300 {
+				status = "okay";
+			};
+
+			usb-phy@47401b00 {
+				status = "okay";
+			};
+
+			usb@47401000 {
+				status = "okay";
+			};
+
+			usb@47401800 {
+				status = "okay";
+				dr_mode = "host";
+			};
+
+			dma-controller@07402000  {
+				status = "okay";
+			};
+		};
+
+		i2c0: i2c@44e0b000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+
+			status = "okay";
+			clock-frequency = <400000>;
+
+			tps: tps@24 {
+				reg = <0x24>;
+			};
+
+		};
+	};
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds_s0>;
+
+		compatible = "gpio-leds";
+
+		led@2 {
+			label = "beaglebone:green:heartbeat";
+			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "beaglebone:green:mmc0";
+			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "beaglebone:green:usr2";
+			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "beaglebone:green:usr3";
+			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+	regulators {
+		dcdc1_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		dcdc2_reg: regulator@1 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1325000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3_reg: regulator@2 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <925000>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		ldo1_reg: regulator@3 {
+			regulator-always-on;
+		};
+
+		ldo2_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		ldo3_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		ldo4_reg: regulator@6 {
+			regulator-always-on;
+		};
+	};
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "mii";
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+};

arch/arm/dts/am335x-boneblack.dts

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+&ldo3_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};

arch/arm/dts/am33xx.dtsi

@@ -0,0 +1,649 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "ti,am33xx";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		d_can0 = &dcan0;
+		d_can1 = &dcan1;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		phy0 = &usb0_phy;
+		phy1 = &usb1_phy;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "arm,cortex-a8";
+			device_type = "cpu";
+			reg = <0>;
+
+			/*
+			 * To consider voltage drop between PMIC and SoC,
+			 * tolerance value is reduced to 2% from 4% and
+			 * voltage value is increased as a precaution.
+			 */
+			operating-points = <
+				/* kHz    uV */
+				720000  1285000
+				600000  1225000
+				500000  1125000
+				275000  1125000
+			>;
+			voltage-tolerance = <2>; /* 2 percentage */
+			clock-latency = <300000>; /* From omap-cpufreq driver */
+		};
+	};
+
+	/*
+	 * The soc node represents the soc top level view. It is uses for IPs
+	 * that are not memory mapped in the MPU view or for the MPU itself.
+	 */
+	soc {
+		compatible = "ti,omap-infra";
+		mpu {
+			compatible = "ti,omap3-mpu";
+			ti,hwmods = "mpu";
+		};
+	};
+
+	am33xx_pinmux: pinmux@44e10800 {
+		compatible = "pinctrl-single";
+		reg = <0x44e10800 0x0238>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7f>;
+	};
+
+	/*
+	 * XXX: Use a flat representation of the AM33XX interconnect.
+	 * The real AM33XX interconnect network is quite complex.Since
+	 * that will not bring real advantage to represent that in DT
+	 * for the moment, just use a fake OCP bus entry to represent
+	 * the whole bus hierarchy.
+	 */
+	ocp {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		ti,hwmods = "l3_main";
+
+		intc: interrupt-controller@48200000 {
+			compatible = "ti,omap2-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,intc-size = <128>;
+			reg = <0x48200000 0x1000>;
+		};
+
+		gpio0: gpio@44e07000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio1";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x44e07000 0x1000>;
+			interrupts = <96>;
+		};
+
+		gpio1: gpio@4804c000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio2";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x4804c000 0x1000>;
+			interrupts = <98>;
+		};
+
+		gpio2: gpio@481ac000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio3";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x481ac000 0x1000>;
+			interrupts = <32>;
+		};
+
+		gpio3: gpio@481ae000 {
+			compatible = "ti,omap4-gpio";
+			ti,hwmods = "gpio4";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			reg = <0x481ae000 0x1000>;
+			interrupts = <62>;
+		};
+
+		uart0: serial@44e09000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart1";
+			clock-frequency = <48000000>;
+			reg = <0x44e09000 0x2000>;
+			interrupts = <72>;
+			status = "disabled";
+		};
+
+		uart1: serial@48022000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart2";
+			clock-frequency = <48000000>;
+			reg = <0x48022000 0x2000>;
+			interrupts = <73>;
+			status = "disabled";
+		};
+
+		uart2: serial@48024000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart3";
+			clock-frequency = <48000000>;
+			reg = <0x48024000 0x2000>;
+			interrupts = <74>;
+			status = "disabled";
+		};
+
+		uart3: serial@481a6000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart4";
+			clock-frequency = <48000000>;
+			reg = <0x481a6000 0x2000>;
+			interrupts = <44>;
+			status = "disabled";
+		};
+
+		uart4: serial@481a8000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart5";
+			clock-frequency = <48000000>;
+			reg = <0x481a8000 0x2000>;
+			interrupts = <45>;
+			status = "disabled";
+		};
+
+		uart5: serial@481aa000 {
+			compatible = "ti,omap3-uart";
+			ti,hwmods = "uart6";
+			clock-frequency = <48000000>;
+			reg = <0x481aa000 0x2000>;
+			interrupts = <46>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@44e0b000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c1";
+			reg = <0x44e0b000 0x1000>;
+			interrupts = <70>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@4802a000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c2";
+			reg = <0x4802a000 0x1000>;
+			interrupts = <71>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@4819c000 {
+			compatible = "ti,omap4-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "i2c3";
+			reg = <0x4819c000 0x1000>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		wdt2: wdt@44e35000 {
+			compatible = "ti,omap3-wdt";
+			ti,hwmods = "wd_timer2";
+			reg = <0x44e35000 0x1000>;
+			interrupts = <91>;
+		};
+
+		dcan0: d_can@481cc000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can0";
+			reg = <0x481cc000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <52>;
+			status = "disabled";
+		};
+
+		dcan1: d_can@481d0000 {
+			compatible = "bosch,d_can";
+			ti,hwmods = "d_can1";
+			reg = <0x481d0000 0x2000
+				0x44e10644 0x4>;
+			interrupts = <55>;
+			status = "disabled";
+		};
+
+		timer1: timer@44e31000 {
+			compatible = "ti,am335x-timer-1ms";
+			reg = <0x44e31000 0x400>;
+			interrupts = <67>;
+			ti,hwmods = "timer1";
+			ti,timer-alwon;
+		};
+
+		timer2: timer@48040000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48040000 0x400>;
+			interrupts = <68>;
+			ti,hwmods = "timer2";
+		};
+
+		timer3: timer@48042000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48042000 0x400>;
+			interrupts = <69>;
+			ti,hwmods = "timer3";
+		};
+
+		timer4: timer@48044000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48044000 0x400>;
+			interrupts = <92>;
+			ti,hwmods = "timer4";
+			ti,timer-pwm;
+		};
+
+		timer5: timer@48046000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48046000 0x400>;
+			interrupts = <93>;
+			ti,hwmods = "timer5";
+			ti,timer-pwm;
+		};
+
+		timer6: timer@48048000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x48048000 0x400>;
+			interrupts = <94>;
+			ti,hwmods = "timer6";
+			ti,timer-pwm;
+		};
+
+		timer7: timer@4804a000 {
+			compatible = "ti,am335x-timer";
+			reg = <0x4804a000 0x400>;
+			interrupts = <95>;
+			ti,hwmods = "timer7";
+			ti,timer-pwm;
+		};
+
+		rtc@44e3e000 {
+			compatible = "ti,da830-rtc";
+			reg = <0x44e3e000 0x1000>;
+			interrupts = <75
+				      76>;
+			ti,hwmods = "rtc";
+		};
+
+		spi0: spi@48030000 {
+			compatible = "ti,omap4-mcspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x48030000 0x400>;
+			interrupts = <65>;
+			ti,spi-num-cs = <2>;
+			ti,hwmods = "spi0";
+			status = "disabled";
+		};
+
+		spi1: spi@481a0000 {
+			compatible = "ti,omap4-mcspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x481a0000 0x400>;
+			interrupts = <125>;
+			ti,spi-num-cs = <2>;
+			ti,hwmods = "spi1";
+			status = "disabled";
+		};
+
+		usb: usb@47400000 {
+			compatible = "ti,am33xx-usb";
+			reg = <0x47400000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ti,hwmods = "usb_otg_hs";
+			status = "disabled";
+
+			ctrl_mod: control@44e10000 {
+				compatible = "ti,am335x-usb-ctrl-module";
+				reg = <0x44e10620 0x10
+					0x44e10648 0x4>;
+				reg-names = "phy_ctrl", "wakeup";
+				status = "disabled";
+			};
+
+			usb0_phy: usb-phy@47401300 {
+				compatible = "ti,am335x-usb-phy";
+				reg = <0x47401300 0x100>;
+				reg-names = "phy";
+				status = "disabled";
+				ti,ctrl_mod = <&ctrl_mod>;
+			};
+
+			usb0: usb@47401000 {
+				compatible = "ti,musb-am33xx";
+				status = "disabled";
+				reg = <0x47401400 0x400
+					0x47401000 0x200>;
+				reg-names = "mc", "control";
+
+				interrupts = <18>;
+				interrupt-names = "mc";
+				dr_mode = "otg";
+				mentor,multipoint = <1>;
+				mentor,num-eps = <16>;
+				mentor,ram-bits = <12>;
+				mentor,power = <500>;
+				phys = <&usb0_phy>;
+
+				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+					&cppi41dma  2 0 &cppi41dma  3 0
+					&cppi41dma  4 0 &cppi41dma  5 0
+					&cppi41dma  6 0 &cppi41dma  7 0
+					&cppi41dma  8 0 &cppi41dma  9 0
+					&cppi41dma 10 0 &cppi41dma 11 0
+					&cppi41dma 12 0 &cppi41dma 13 0
+					&cppi41dma 14 0 &cppi41dma  0 1
+					&cppi41dma  1 1 &cppi41dma  2 1
+					&cppi41dma  3 1 &cppi41dma  4 1
+					&cppi41dma  5 1 &cppi41dma  6 1
+					&cppi41dma  7 1 &cppi41dma  8 1
+					&cppi41dma  9 1 &cppi41dma 10 1
+					&cppi41dma 11 1 &cppi41dma 12 1
+					&cppi41dma 13 1 &cppi41dma 14 1>;
+				dma-names =
+					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+					"rx14", "rx15",
+					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+					"tx14", "tx15";
+			};
+
+			usb1_phy: usb-phy@47401b00 {
+				compatible = "ti,am335x-usb-phy";
+				reg = <0x47401b00 0x100>;
+				reg-names = "phy";
+				status = "disabled";
+				ti,ctrl_mod = <&ctrl_mod>;
+			};
+
+			usb1: usb@47401800 {
+				compatible = "ti,musb-am33xx";
+				status = "disabled";
+				reg = <0x47401c00 0x400
+					0x47401800 0x200>;
+				reg-names = "mc", "control";
+				interrupts = <19>;
+				interrupt-names = "mc";
+				dr_mode = "otg";
+				mentor,multipoint = <1>;
+				mentor,num-eps = <16>;
+				mentor,ram-bits = <12>;
+				mentor,power = <500>;
+				phys = <&usb1_phy>;
+
+				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+					&cppi41dma 17 0 &cppi41dma 18 0
+					&cppi41dma 19 0 &cppi41dma 20 0
+					&cppi41dma 21 0 &cppi41dma 22 0
+					&cppi41dma 23 0 &cppi41dma 24 0
+					&cppi41dma 25 0 &cppi41dma 26 0
+					&cppi41dma 27 0 &cppi41dma 28 0
+					&cppi41dma 29 0 &cppi41dma 15 1
+					&cppi41dma 16 1 &cppi41dma 17 1
+					&cppi41dma 18 1 &cppi41dma 19 1
+					&cppi41dma 20 1 &cppi41dma 21 1
+					&cppi41dma 22 1 &cppi41dma 23 1
+					&cppi41dma 24 1 &cppi41dma 25 1
+					&cppi41dma 26 1 &cppi41dma 27 1
+					&cppi41dma 28 1 &cppi41dma 29 1>;
+				dma-names =
+					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+					"rx14", "rx15",
+					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+					"tx14", "tx15";
+			};
+
+			cppi41dma: dma-controller@07402000 {
+				compatible = "ti,am3359-cppi41";
+				reg =  <0x47400000 0x1000
+					0x47402000 0x1000
+					0x47403000 0x1000
+					0x47404000 0x4000>;
+				reg-names = "glue", "controller", "scheduler", "queuemgr";
+				interrupts = <17>;
+				interrupt-names = "glue";
+				#dma-cells = <2>;
+				#dma-channels = <30>;
+				#dma-requests = <256>;
+				status = "disabled";
+			};
+		};
+
+		epwmss0: epwmss@48300000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48300000 0x10>;
+			ti,hwmods = "epwmss0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+				  0x48300180 0x48300180 0x80   /* EQEP */
+				  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+			ecap0: ecap@48300100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48300100 0x80>;
+				ti,hwmods = "ecap0";
+				status = "disabled";
+			};
+
+			ehrpwm0: ehrpwm@48300200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48300200 0x80>;
+				ti,hwmods = "ehrpwm0";
+				status = "disabled";
+			};
+		};
+
+		epwmss1: epwmss@48302000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48302000 0x10>;
+			ti,hwmods = "epwmss1";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+				  0x48302180 0x48302180 0x80   /* EQEP */
+				  0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+			ecap1: ecap@48302100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48302100 0x80>;
+				ti,hwmods = "ecap1";
+				status = "disabled";
+			};
+
+			ehrpwm1: ehrpwm@48302200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48302200 0x80>;
+				ti,hwmods = "ehrpwm1";
+				status = "disabled";
+			};
+		};
+
+		epwmss2: epwmss@48304000 {
+			compatible = "ti,am33xx-pwmss";
+			reg = <0x48304000 0x10>;
+			ti,hwmods = "epwmss2";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+			ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+				  0x48304180 0x48304180 0x80   /* EQEP */
+				  0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+			ecap2: ecap@48304100 {
+				compatible = "ti,am33xx-ecap";
+				#pwm-cells = <3>;
+				reg = <0x48304100 0x80>;
+				ti,hwmods = "ecap2";
+				status = "disabled";
+			};
+
+			ehrpwm2: ehrpwm@48304200 {
+				compatible = "ti,am33xx-ehrpwm";
+				#pwm-cells = <3>;
+				reg = <0x48304200 0x80>;
+				ti,hwmods = "ehrpwm2";
+				status = "disabled";
+			};
+		};
+
+		mac: ethernet@4a100000 {
+			compatible = "ti,cpsw";
+			ti,hwmods = "cpgmac0";
+			cpdma_channels = <8>;
+			ale_entries = <1024>;
+			bd_ram_size = <0x2000>;
+			no_bd_ram = <0>;
+			rx_descs = <64>;
+			mac_control = <0x20>;
+			slaves = <2>;
+			active_slave = <0>;
+			cpts_clock_mult = <0x80000000>;
+			cpts_clock_shift = <29>;
+			reg = <0x4a100000 0x800
+			       0x4a101200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-parent = <&intc>;
+			/*
+			 * c0_rx_thresh_pend
+			 * c0_rx_pend
+			 * c0_tx_pend
+			 * c0_misc_pend
+			 */
+			interrupts = <40 41 42 43>;
+			ranges;
+
+			davinci_mdio: mdio@4a101000 {
+				compatible = "ti,davinci_mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ti,hwmods = "davinci_mdio";
+				bus_freq = <1000000>;
+				reg = <0x4a101000 0x100>;
+			};
+
+			cpsw_emac0: slave@4a100200 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+
+			cpsw_emac1: slave@4a100300 {
+				/* Filled in by U-Boot */
+				mac-address = [ 00 00 00 00 00 00 ];
+			};
+		};
+
+		ocmcram: ocmcram@40300000 {
+			compatible = "ti,am3352-ocmcram";
+			reg = <0x40300000 0x10000>;
+			ti,hwmods = "ocmcram";
+		};
+
+		wkup_m3: wkup_m3@44d00000 {
+			compatible = "ti,am3353-wkup-m3";
+			reg = <0x44d00000 0x4000	/* M3 UMEM */
+			       0x44d80000 0x2000>;	/* M3 DMEM */
+			ti,hwmods = "wkup_m3";
+		};
+
+		elm: elm@48080000 {
+			compatible = "ti,am3352-elm";
+			reg = <0x48080000 0x2000>;
+			interrupts = <4>;
+			ti,hwmods = "elm";
+			status = "disabled";
+		};
+
+		tscadc: tscadc@44e0d000 {
+			compatible = "ti,am3359-tscadc";
+			reg = <0x44e0d000 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <16>;
+			ti,hwmods = "adc_tsc";
+			status = "disabled";
+
+			tsc {
+				compatible = "ti,am3359-tsc";
+			};
+			am335x_adc: adc {
+				#io-channel-cells = <1>;
+				compatible = "ti,am3359-adc";
+			};
+		};
+
+		gpmc: gpmc@50000000 {
+			compatible = "ti,am3352-gpmc";
+			ti,hwmods = "gpmc";
+			reg = <0x50000000 0x2000>;
+			interrupts = <100>;
+			gpmc,num-cs = <7>;
+			gpmc,num-waitpins = <2>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+	};
+};

arch/arm/dts/dt-bindings/gpio/gpio.h

@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif

arch/arm/dts/dt-bindings/pinctrl/am33xx.h

@@ -0,0 +1,42 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE		(1 << 3)
+#define INPUT_EN		(1 << 5)
+#define SLEWCTRL_FAST		(1 << 6)
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+

arch/arm/dts/dt-bindings/pinctrl/omap.h

@@ -0,0 +1,55 @@
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
+#endif
+

arch/arm/dts/include/dt-bindings

@@ -0,0 +1 @@
+../../../../include/dt-bindings

arch/arm/dts/tegra114.dtsi

@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
@@ -46,17 +49,17 @@
 			      0 143 0x04>;
 	};
 
-	gpio: gpio {
+	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04
-			      0 125 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;

arch/arm/dts/tegra124.dtsi

@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
@@ -49,14 +52,14 @@
 	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04
-			      0 125 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;

arch/arm/dts/tegra20.dtsi

@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
@@ -139,10 +142,18 @@
 
 	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra20-gpio";
-		reg = < 0x6000d000 0x1000 >;
-		interrupts = < 64 65 66 67 87 119 121 >;
+		reg = <0x6000d000 0x1000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
 	};
 
 	pinmux: pinmux@70000000 {

arch/arm/dts/tegra30.dtsi

@@ -1,3 +1,6 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 #include "skeleton.dtsi"
 
 / {
@@ -47,17 +50,17 @@
 		clocks = <&tegra_car 34>;
 	};
 
-	gpio: gpio {
+	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-		interrupts = <0 32 0x04
-			      0 33 0x04
-			      0 34 0x04
-			      0 35 0x04
-			      0 55 0x04
-			      0 87 0x04
-			      0 89 0x04
-			      0 125 0x04>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 		#gpio-cells = <2>;
 		gpio-controller;
 		#interrupt-cells = <2>;

arch/arm/dts/tps65217.dtsi

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+	compatible = "ti,tps65217";
+
+	regulators {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dcdc1_reg: regulator@0 {
+			reg = <0>;
+			regulator-compatible = "dcdc1";
+		};
+
+		dcdc2_reg: regulator@1 {
+			reg = <1>;
+			regulator-compatible = "dcdc2";
+		};
+
+		dcdc3_reg: regulator@2 {
+			reg = <2>;
+			regulator-compatible = "dcdc3";
+		};
+
+		ldo1_reg: regulator@3 {
+			reg = <3>;
+			regulator-compatible = "ldo1";
+		};
+
+		ldo2_reg: regulator@4 {
+			reg = <4>;
+			regulator-compatible = "ldo2";
+		};
+
+		ldo3_reg: regulator@5 {
+			reg = <5>;
+			regulator-compatible = "ldo3";
+		};
+
+		ldo4_reg: regulator@6 {
+			reg = <6>;
+			regulator-compatible = "ldo4";
+		};
+	};
+};

arch/arm/imx-common/Makefile

@@ -33,10 +33,6 @@ $(IMX_CONFIG): %.cfgtmp: % FORCE
 	$(Q)mkdir -p $(dir $@)
 	$(call if_changed_dep,cpp_cfg)
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
 	-e $(CONFIG_SYS_TEXT_BASE)
 

arch/arm/include/asm/atomic.h

@@ -25,7 +25,7 @@ typedef struct { volatile int counter; } atomic_t;
 #define ATOMIC_INIT(i)	{ (i) }
 
 #ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define atomic_read(v)	((v)->counter)
 #define atomic_set(v,i)	(((v)->counter) = (i))

arch/arm/include/asm/bitops.h

@@ -17,7 +17,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
 
 #define smp_mb__before_clear_bit()	do { } while (0)
 #define smp_mb__after_clear_bit()	do { } while (0)

arch/arm/include/asm/io.h

@@ -437,4 +437,7 @@ out:
 
 #endif	/* __mem_isa */
 #endif	/* __KERNEL__ */
+
+#include <iotrace.h>
+
 #endif	/* __ASM_ARM_IO_H */

arch/arm/include/asm/proc-armv/processor.h

@@ -18,7 +18,7 @@
 #ifndef __ASM_PROC_PROCESSOR_H
 #define __ASM_PROC_PROCESSOR_H
 
-#include <asm/proc/domain.h>
+#include <asm/proc-armv/domain.h>
 
 #define KERNEL_STACK_SIZE	PAGE_SIZE
 

arch/arm/include/asm/processor.h

@@ -45,7 +45,7 @@ typedef unsigned long mm_segment_t;		/* domain register	*/
 #if 0	/* XXX###XXX */
 #include <asm/arch/memory.h>
 #endif	/* XXX###XXX */
-#include <asm/proc/processor.h>
+#include <asm/proc-armv/processor.h>
 #include <asm/types.h>
 
 union debug_insn {

arch/arm/include/asm/ptrace.h

@@ -11,7 +11,7 @@
 /* options set using PTRACE_SETOPTIONS */
 #define PTRACE_O_TRACESYSGOOD	0x00000001
 
-#include <asm/proc/ptrace.h>
+#include <asm/proc-armv/ptrace.h>
 
 #ifndef __ASSEMBLY__
 #define pc_pointer(v) \

arch/arm/lib/board.c

@@ -277,7 +277,7 @@ void board_init_f(ulong bootflag)
 	gd->mon_len = (ulong)&__bss_end - (ulong)_start;
 #ifdef CONFIG_OF_EMBED
 	/* Get a pointer to the FDT */
-	gd->fdt_blob = __dtb_db_begin;
+	gd->fdt_blob = __dtb_dt_begin;
 #elif defined CONFIG_OF_SEPARATE
 	/* FDT is at end of image */
 	gd->fdt_blob = &_end;

arch/m68k/cpu/mcf532x/cpu_init.c

@@ -208,10 +208,10 @@ void cpu_init_f(void)
 	scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+#ifndef CONFIG_WATCHDOG
 	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
 
 	/* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
 	out_be16(&wdog->cr, 0);
 #endif
 

arch/m68k/cpu/mcf5445x/cpu_init.c

@@ -364,9 +364,9 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
-#ifdef CONFIG_MCF5445x
 	if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)

arch/m68k/include/asm/io.h

@@ -32,10 +32,10 @@
 #define writew(b,addr)		((*(volatile u16 *) (addr)) = (b))
 #define writel(b,addr)		((*(volatile u32 *) (addr)) = (b))
 #else
-#define readw(addr)		in_le16((volatile u16 *)(addr))
-#define readl(addr)		in_le32((volatile u32 *)(addr))
-#define writew(b,addr)		out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr)		out_le32((volatile u32 *)(addr),(b))
+#define readw(addr)		in_be16((volatile u16 *)(addr))
+#define readl(addr)		in_be32((volatile u32 *)(addr))
+#define writew(b,addr)		out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr)		out_be32((volatile u32 *)(addr),(b))
 #endif
 
 /*

arch/m68k/include/asm/posix_types.h

@@ -15,7 +15,7 @@ typedef long		__kernel_off_t;
 typedef int		__kernel_pid_t;
 typedef unsigned int	__kernel_uid_t;
 typedef unsigned int	__kernel_gid_t;
-typedef unsigned int	__kernel_size_t;
+typedef unsigned long	__kernel_size_t;
 typedef int		__kernel_ssize_t;
 typedef long		__kernel_ptrdiff_t;
 typedef long		__kernel_time_t;

arch/m68k/lib/board.c

@@ -31,9 +31,6 @@
 #endif
 #include <net.h>
 #include <serial.h>
-#if defined(CONFIG_CMD_BEDBUG)
-#include <cmd_bedbug.h>
-#endif
 #ifdef CONFIG_SYS_ALLOC_DPRAM
 #include <commproc.h>
 #endif
@@ -602,11 +599,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	last_stage_init ();
 #endif
 
-#if defined(CONFIG_CMD_BEDBUG)
-	WATCHDOG_RESET ();
-	bedbug_init ();
-#endif
-
 #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
 	/*
 	 * Export available size of memory for Linux,
@@ -628,13 +620,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	}
 #endif
 
-#ifdef CONFIG_MODEM_SUPPORT
- {
-	 extern int do_mdm_init;
-	 do_mdm_init = gd->do_mdm_init;
- }
-#endif
-
 #ifdef CONFIG_WATCHDOG
 	/* disable watchdog if environment is set */
 	if ((s = getenv ("watchdog")) != NULL) {

arch/m68k/lib/bootm.c

@@ -50,11 +50,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
-	ulong rd_len;
-	ulong initrd_start, initrd_end;
 	int ret;
-
-	ulong cmd_start, cmd_end;
 	bd_t  *kbd;
 	void  (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
 	struct lmb *lmb = &images->lmb;
@@ -96,7 +92,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 	 *   sp+16: Start of command line string
 	 *   sp+20: End   of command line string
 	 */
-	(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+	(*kernel)(kbd, images->initrd_start, images->initrd_end,
+		  images->cmdline_start, images->cmdline_end);
 	/* does not return */
 error:
 	return 1;

arch/microblaze/dts/include/dt-bindings

@@ -0,0 +1 @@
+../../../../include/dt-bindings

arch/microblaze/lib/bootm.c

@@ -58,7 +58,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
 	/* fixup the initrd now that we know where it should be */
 	if (images->rd_start && images->rd_end && of_flat_tree)
 		ret = fdt_initrd(of_flat_tree, images->rd_start,
-				 images->rd_end, 1);
+				 images->rd_end);
 		if (ret)
 			return 1;
 

arch/openrisc/cpu/start.S

@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -40,9 +41,48 @@ __reset:
 	l.ori	r3,r0,SPR_SR_SM
 	l.mtspr	r0,r3,SPR_SR
 
+	l.jal	_cur
+	l.nop
+_cur:
+	l.ori	r8, r9, 0		/* Get _cur current address */
+
+	l.movhi	r3, hi(_cur)
+	l.ori	r3, r3, lo(_cur)
+	l.sfeq	r8, r3			/* If we are running at the linked address */
+	l.bf	_no_vector_reloc	/* there is not need for relocation */
+	 l.sub	r8, r8, r3
+
+	l.mfspr	r4, r0, SPR_CPUCFGR
+	l.andi	r4, r4, SPR_CPUCFGR_EVBARP	/* Exception Vector Base Address Register present ? */
+	l.sfnei	r4,0
+	l.bnf	_reloc_vectors
+	l.movhi	r5, 0			/* Destination */
+
+	l.mfspr	r4, r0, SPR_EVBAR
+	l.add	r5, r5, r4
+
+_reloc_vectors:
+	/* Relocate vectors*/
+	l.movhi	r5, 0			/* Destination */
+	l.movhi	r6, hi(__start)		/* Length */
+	l.ori	r6, r6, lo(__start)
+	l.ori	r3, r8, 0
+
+.L_relocvectors:
+	l.lwz	r7, 0(r3)
+	l.sw	0(r5), r7
+	l.addi	r5, r5, 4
+	l.sfeq	r5, r6
+	l.bnf	.L_relocvectors
+	 l.addi	r3, r3, 4
+
+_no_vector_reloc:
+
 	/* Relocate u-boot */
-	l.movhi	r3,hi(__start)		/* source start address */
+	l.movhi	r3,hi(__start)		/* source start offset */
 	l.ori	r3,r3,lo(__start)
+	l.add	r3,r8,r3
+
 	l.movhi	r4,hi(_stext)		/* dest start address */
 	l.ori	r4,r4,lo(_stext)
 	l.movhi	r5,hi(__end)		/* dest end address */
@@ -56,19 +96,6 @@ __reset:
 	l.bf	.L_reloc
 	 l.addi	r4,r4,4			/* delay slot */
 
-#ifdef CONFIG_SYS_RELOCATE_VECTORS
-	/* Relocate vectors from 0xf0000000 to 0x00000000 */
-	l.movhi r4, 0xf000 /* source */
-	l.movhi r5, 0      /* destination */
-	l.addi	r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
-.L_relocvectors:
-	l.lwz	r7, 0(r4)
-	l.sw	0(r5), r7
-	l.addi	r5, r5, 4
-	l.sfeq	r5,r6
-	l.bnf	.L_relocvectors
-	 l.addi	r4,r4, 4
-#endif
 	l.movhi	r4,hi(_start)
 	l.ori	r4,r4,lo(_start)
 	l.jr	r4

arch/openrisc/include/asm/spr-defs.h

@@ -46,6 +46,11 @@
 #define SPR_ICCFGR	(SPRGROUP_SYS + 6)
 #define SPR_DCFGR	(SPRGROUP_SYS + 7)
 #define SPR_PCCFGR	(SPRGROUP_SYS + 8)
+#define SPR_VR2		(SPRGROUP_SYS + 9)
+#define SPR_AVR		(SPRGROUP_SYS + 10)
+#define SPR_EVBAR	(SPRGROUP_SYS + 11)
+#define SPR_AECR	(SPRGROUP_SYS + 12)
+#define SPR_AESR	(SPRGROUP_SYS + 13)
 #define SPR_NPC		(SPRGROUP_SYS + 16)
 #define SPR_SR		(SPRGROUP_SYS + 17)
 #define SPR_PPC		(SPRGROUP_SYS + 18)
@@ -161,7 +166,13 @@
 #define SPR_CPUCFGR_OF32S	0x00000080 /* ORFPX32 supported */
 #define SPR_CPUCFGR_OF64S	0x00000100 /* ORFPX64 supported */
 #define SPR_CPUCFGR_OV64S	0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES		0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND		0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP	0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP	0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP	0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP	0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+					   /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES		0xffffc000 /* Reserved */
 
 /*
  * Bit definitions for the Debug configuration register and other

arch/powerpc/cpu/mpc8260/pci.c

@@ -242,8 +242,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
 	immap->im_siu_conf.sc_siumcr =
 		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 		| SIUMCR_LBPC01;
-#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/* nothing to do for this board here */
 #elif defined CONFIG_MPC8272
 	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
 				  ~SIUMCR_BBD &

arch/powerpc/cpu/mpc8260/start.S

@@ -137,19 +137,6 @@ _hrcw_table:
 
 	.globl	_start
 _start:
-#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
-	lis	r3, CONFIG_SYS_DEFAULT_IMMR@h
-	nop
-	lwz	r4, 0(r3)
-	nop
-	rlwinm	r4, r4, 0, 8, 5
-	nop
-	oris	r4, r4, 0x0200
-	nop
-	stw	r4, 0(r3)
-	nop
-#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-
 	mfmsr	r5			/* save msr contents		*/
 
 #if defined(CONFIG_COGENT)

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+	puts("Work-around for Erratum A004508 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	puts("Work-around for Erratum A004510 enabled\n");
 #endif
@@ -266,6 +269,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 	puts("Work-around for Erratum USB14 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	puts("Work-around for Erratum A007186 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 	puts("Work-around for Erratum A006593 enabled\n");
 #endif

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -225,6 +225,32 @@ static void disable_cpc_sram(void)
 }
 #endif
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+	int ret;
+	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+	int tdm_hwconfig_enabled = 0;
+
+	/*
+	 * Extract hwconfig from environment since environment
+	 * is not setup properly yet. Search for tdm entry in
+	 * hwconfig.
+	 */
+	ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (ret > 0) {
+		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+		/* If tdm is defined in hwconfig, set law for tdm workaround */
+		if (tdm_hwconfig_enabled)
+			set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+				     LAW_TRGT_IF_CCSR);
+	}
+}
+#endif
+
 static void enable_cpc(void)
 {
 	int i;
@@ -729,6 +755,9 @@ skip_l2:
 	disable_cpc_sram();
 #endif
 	enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+	enable_tdm_law();
+#endif
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	/* needs to be in ram since code uses global static vars */

arch/powerpc/cpu/mpc85xx/fdt.c

@@ -14,6 +14,7 @@
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_portals.h>
+#include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
@@ -35,6 +36,11 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 id = get_my_id();
 	const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+	int ret;
+	int tdm_hwconfig_enabled = 0;
+	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
 
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
@@ -77,6 +83,26 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 				"device_type", "cpu", 4);
 	}
 
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define	CONFIG_MEM_HOLE_16M	0x1000000
+	/*
+	 * Extract hwconfig from environment.
+	 * Search for tdm entry in hwconfig.
+	 */
+	ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+	if (ret > 0)
+		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+	/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+	if (tdm_hwconfig_enabled) {
+		off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+				      CONFIG_MEM_HOLE_16M);
+		if (off < 0)
+			printf("Failed  to reserve memory for tdm: %s\n",
+			       fdt_strerror(off));
+	}
+#endif
+
 	/* Reserve the boot page so OSes dont use it */
 	if ((u64)bootpg < memory_limit) {
 		off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);

arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c

@@ -147,12 +147,43 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 	return -ENODEV;
 }
 
+#define BC3_SHIFT	9
+#define DC3_SHIFT	6
+#define FC3_SHIFT	0
+#define BC2_SHIFT	19
+#define DC2_SHIFT	16
+#define FC2_SHIFT	10
+#define BC1_SHIFT	29
+#define DC1_SHIFT	26
+#define FC1_SHIFT	20
+#define BC_MASK		0x1
+#define DC_MASK		0x7
+#define FC_MASK		0x3F
+
+#define FUSE_VAL_MASK		0x00000003
+#define FUSE_VAL_SHIFT		30
+#define CR0_DCBIAS_SHIFT	5
+#define CR1_FCAP_SHIFT		15
+#define CR1_BCAP_SHIFT		29
+#define FCAP_MASK		0x001F8000
+#define BCAP_MASK		0x20000000
+#define BCAP_OVD_MASK		0x10000000
+#define BYP_CAL_MASK		0x02000000
+
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	struct ccsr_sfp_regs  __iomem *sfp_regs =
+			(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+	u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+	u32 bc_status, fc_status, dc_status, pll_sr2;
+	serdes_corenet_t  __iomem *srds_regs = (void *)sd_addr;
+	u32 sfp_spfr0, sel;
+#endif
 
 	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
 	/* Is serdes enabled at all? */
@@ -161,6 +192,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 		return 0;
 	}
 
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+	sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+	debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+	sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+	if (sel == 0x01 || sel == 0x02) {
+		for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+			pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			debug("A007186: pll_num=%x pllcr0=%x\n",
+			      pll_num, pll_status);
+			/* STEP 1 */
+			/* Read factory pre-set SerDes calibration values
+			 * from fuse block(SFP scratch register-sfp_spfr0)
+			 */
+			switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+			case SRDS_PLLCR0_FRATE_SEL_3_0:
+			case SRDS_PLLCR0_FRATE_SEL_3_072:
+				debug("A007186: 3.0/3.072 protocol rate\n");
+				bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+				break;
+			case SRDS_PLLCR0_FRATE_SEL_3_125:
+				debug("A007186: 3.125 protocol rate\n");
+				bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+				break;
+			case SRDS_PLLCR0_FRATE_SEL_3_75:
+				debug("A007186: 3.75 protocol rate\n");
+				bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+				dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+				fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+				break;
+			default:
+				continue;
+			}
+
+			/* STEP 2 */
+			/* Write SRDSxPLLnCR1[11:16] = FC
+			 * Write SRDSxPLLnCR1[2] = BC
+			 */
+			pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+			pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+				      ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+				 (pll_cr_upd | pll_cr1));
+			debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+			      pll_num, (pll_cr_upd | pll_cr1));
+			/* Write SRDSxPLLnCR0[24:26] = DC
+			 */
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0,
+				 pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+			debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+			      pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+			/* Write SRDSxPLLnCR1[3] = 1
+			 * Write SRDSxPLLnCR1[6] = 1
+			 */
+			pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+			pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+			out_be32(&srds_regs->bank[pll_num].pllcr1,
+				 (pll_cr_upd | pll_cr1));
+			debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+			      pll_num, (pll_cr_upd | pll_cr1));
+
+			/* STEP 3 */
+			/* Read the status Registers */
+			/* Verify SRDSxPLLnSR2[8] = BC */
+			pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+			debug("A007186: pll_num=%x pllsr2=%x\n",
+			      pll_num, pll_sr2);
+			bc_status = (pll_sr2 >> 23) & BC_MASK;
+			if (bc_status != bc)
+				debug("BC mismatch\n");
+			fc_status = (pll_sr2 >> 16) & FC_MASK;
+			if (fc_status != fc)
+				debug("FC mismatch\n");
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+								0x02000000);
+			pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+			dc_status = (pll_sr2 >> 17) & DC_MASK;
+			if (dc_status != dc)
+				debug("DC mismatch\n");
+			pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+								0xfdffffff);
+
+			/* STEP 4 */
+			/* Wait 750us to verify the PLL is locked
+			 * by checking SRDSxPLLnCR0[8] = 1.
+			 */
+			udelay(750);
+			pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+			debug("A007186: pll_num=%x pllcr0=%x\n",
+			      pll_num, pll_status);
+
+			if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+				printf("A007186 Serdes PLL not locked\n");
+			else
+				debug("A007186 Serdes PLL locked\n");
+		}
+	}
+#endif
+
 	cfg >>= sd_prctl_shift;
 	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 	if (!is_serdes_prtcl_valid(sd, cfg))

arch/powerpc/cpu/mpc85xx/t1040_ids.c

@@ -47,6 +47,7 @@ struct liodn_id_table liodn_tbl[] = {
 
 	/* SET_NEXUS_LIODN(557), -- not yet implemented */
 	SET_QE_LIODN(559),
+	SET_TDM_LIODN(560),
 };
 int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 

arch/powerpc/cpu/mpc85xx/t2080_serdes.c

@@ -43,6 +43,10 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
+	{0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
@@ -59,18 +63,34 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM1_MAC1, XFI_FM1_MAC2,
+		PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, SGMII_FM1_DTSEC4,
@@ -115,6 +135,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+	{0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
 	{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
@@ -127,8 +150,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM1_MAC1, XFI_FM1_MAC2,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
 	{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
 		PCIE4, PCIE4, PCIE4, PCIE4} },
 	{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
@@ -137,7 +158,6 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 	{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
 		SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
 		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
 	{}
 };
 
@@ -150,6 +170,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 	{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+	{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE,  NONE,  SATA1, SATA2} },
 	{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
 	{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },

arch/powerpc/cpu/mpc85xx/t4240_serdes.c

@@ -30,22 +30,41 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		NONE, NONE, QSGMII_FM1_A, NONE}},
@@ -65,10 +84,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
 		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -77,10 +104,18 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -89,6 +124,10 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -97,34 +136,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, QSGMII_FM2_A, NONE} },
+	{55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, XFI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -137,22 +208,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -161,13 +244,21 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
 	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+	{5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+	{11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
 	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+	{13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
 	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
 	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
 	{}
@@ -187,36 +278,66 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
 		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
 	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{}
 };
 static const struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -225,34 +346,66 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		NONE, NONE} },
+	{27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, QSGMII_FM1_A, NONE, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
 		NONE, QSGMII_FM1_A, NONE, NONE} },
+	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, NONE, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		NONE, NONE, NONE, NONE} },
+	{55, {NONE, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, NONE,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{56, {NONE, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, NONE,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -265,22 +418,34 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 };
 static const struct serdes_config serdes3_cfg_tbl[] = {
 	/* SerDes 3 */
+	{1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
 	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+	{3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
+	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
+	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -289,12 +454,19 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
+	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
 	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
 	{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+	{11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
 	{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+	{13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
 	{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
 	{}

arch/powerpc/cpu/ppc4xx/cpu.c

@@ -607,9 +607,6 @@ int checkcpu (void)
 #if defined(SDR0_PINSTP_SHIFT)
 	printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
 	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
-#ifdef CONFIG_NAND_U_BOOT
-	puts(", booting from NAND");
-#endif /* CONFIG_NAND_U_BOOT */
 	putc('\n');
 #endif	/* SDR0_PINSTP_SHIFT */
 

arch/powerpc/include/asm/config_mpc85xx.h

@@ -38,6 +38,7 @@
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_MPC8540)
@@ -122,6 +123,7 @@
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_MPC8572)
@@ -132,6 +134,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1010)
@@ -154,6 +157,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x10
@@ -171,6 +175,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1012 is single core version of P1021 */
@@ -188,6 +193,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1013 is single core version of P1022 */
@@ -202,6 +208,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1014)
@@ -219,6 +226,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 
 /* P1017 is single core version of P1023 */
 #elif defined(CONFIG_P1017)
@@ -234,6 +242,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1020)
@@ -246,6 +255,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
@@ -264,6 +274,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
@@ -278,6 +289,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P1023)
@@ -293,6 +305,7 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x11
@@ -309,6 +322,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P1025 is lower end variant of P1021 */
@@ -326,6 +340,7 @@
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 /* P2010 is single core version of P2020 */
@@ -338,6 +353,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_P2020)
@@ -353,8 +369,10 @@
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_RMU
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
@@ -657,8 +675,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
@@ -684,12 +704,14 @@
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007075
 #define CONFIG_SYS_FSL_ERRATUM_A006475
 #define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #ifdef CONFIG_PPC_B4860
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
@@ -809,8 +831,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 
 #elif defined(CONFIG_PPC_C29X)

arch/powerpc/include/asm/fsl_law.h

@@ -68,6 +68,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
 	LAW_TRGT_IF_BMAN = 0x18,
 	LAW_TRGT_IF_DCSR = 0x1d,
+	LAW_TRGT_IF_CCSR = 0x1e,
 	LAW_TRGT_IF_LBC = 0x1f,
 	LAW_TRGT_IF_QMAN = 0x3c,
 

arch/powerpc/include/asm/fsl_liodn.h

@@ -103,6 +103,10 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
 		CONFIG_SYS_MPC85xx_QE_OFFSET)
 
+#define SET_TDM_LIODN(liodn) \
+	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+		CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
 #define SET_QMAN_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \

arch/powerpc/include/asm/immap_85xx.h

@@ -1899,7 +1899,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u32	sata2liodnr;	/* SATA 2 LIODN */
 	u32	sata3liodnr;	/* SATA 3 LIODN */
 	u32	sata4liodnr;	/* SATA 4 LIODN */
-	u8      res22[24];
+	u8	res22[20];
+	u32	tdmliodnr;	/* TDM LIODN */
 	u32     qeliodnr;       /* QE LIODN */
 	u8      res_57c[4];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
@@ -2521,14 +2522,17 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
 #define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_125	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0	0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072	0x000c0000
 #define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
 		u32	pllcr1; /* PLL Control Register 1 */
@@ -2863,6 +2867,21 @@ struct ccsr_pman {
 	u8	res_f4[0xf0c];
 };
 #endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+	u32 ospr;		/* 0x200 */
+	u32 reserved0[14];
+	u32 srk_hash[8];	/* 0x23c Super Root Key Hash */
+	u32 oem_uid;		/* 0x9c OEM Unique ID */
+	u8 reserved2[0x04];
+	u32 ovpr;			/* 0xA4  Intent To Secure */
+	u8 reserved4[0x08];
+	u32 fsl_uid;		/* 0xB0  FSL Unique ID */
+	u8 reserved5[0x04];
+	u32 fsl_spfr0;		/* Scratch Pad Fuse Register 0 */
+	u32 fsl_spfr1;		/* Scratch Pad Fuse Register 1 */
+};
+#endif
 
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
@@ -2876,6 +2895,14 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ *  * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET                  0x200
+#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
@@ -2889,6 +2916,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
@@ -3094,6 +3122,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_PCIE4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 
+#define CONFIG_SYS_SFP_ADDR  \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 

arch/powerpc/include/asm/processor.h

@@ -1346,26 +1346,14 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #if defined(CONFIG_8xx)
 #define _machine _MACH_8xx
 #define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of	0
 #elif defined(CONFIG_WALNUT)
 #define _machine _MACH_walnut
 #define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
 #elif defined(CONFIG_MPC8260)
 #define _machine _MACH_8260
 #define have_of 0
 #elif defined(CONFIG_SANDPOINT)
 #define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
 #else
 #error "Machine not defined correctly"
 #endif

arch/powerpc/lib/board.c

@@ -991,14 +991,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	kbd_init();
 #endif
 
-#ifdef CONFIG_MODEM_SUPPORT
-	{
-		extern int do_mdm_init;
-
-		do_mdm_init = gd->do_mdm_init;
-	}
-#endif
-
 	/* Initialization complete - start the monitor */
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */

arch/sandbox/cpu/os.c

@@ -341,6 +341,7 @@ int os_dirent_ls(const char *dirname, struct os_dirent_node **headp)
 			ret = -ENOMEM;
 			goto done;
 		}
+		next->next = NULL;
 		strcpy(next->name, entry.d_name);
 		switch (entry.d_type) {
 		case DT_REG:

arch/sandbox/dts/include/dt-bindings

@@ -0,0 +1 @@
+../../../../include/dt-bindings

arch/sandbox/include/asm/bitops.h

@@ -17,6 +17,7 @@
 #ifndef __ASM_SANDBOX_BITOPS_H
 #define __ASM_SANDBOX_BITOPS_H
 
+#include <linux/compiler.h>
 #include <asm/system.h>
 
 #ifdef __KERNEL__
@@ -53,7 +54,7 @@ static inline int __test_and_set_bit(int nr, void *addr)
 
 static inline int test_and_set_bit(int nr, void *addr)
 {
-	unsigned long flags;
+	unsigned long __always_unused flags;
 	int out;
 
 	local_irq_save(flags);
@@ -75,7 +76,7 @@ static inline int __test_and_clear_bit(int nr, void *addr)
 
 static inline int test_and_clear_bit(int nr, void *addr)
 {
-	unsigned long flags;
+	unsigned long __always_unused flags;
 	int out;
 
 	local_irq_save(flags);

arch/sandbox/include/asm/gpio.h

@@ -29,7 +29,7 @@
  * @param gp	GPIO number
  * @return -1 on error, 0 if GPIO is low, >0 if high
  */
-int sandbox_gpio_get_value(struct device *dev, unsigned int offset);
+int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
 
 /**
  * Set the simulated value of a GPIO (used only in sandbox test code)
@@ -38,7 +38,7 @@ int sandbox_gpio_get_value(struct device *dev, unsigned int offset);
  * @param value	value to set (0 for low, non-zero for high)
  * @return -1 on error, 0 if ok
  */
-int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value);
+int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
 
 /**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
@@ -46,7 +46,7 @@ int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value);
  * @param gp	GPIO number
  * @return -1 on error, 0 if GPIO is input, >0 if output
  */
-int sandbox_gpio_get_direction(struct device *dev, unsigned int offset);
+int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
 
 /**
  * Set the simulated direction of a GPIO (used only in sandbox test code)
@@ -55,7 +55,7 @@ int sandbox_gpio_get_direction(struct device *dev, unsigned int offset);
  * @param output 0 to set as input, 1 to set as output
  * @return -1 on error, 0 if ok
  */
-int sandbox_gpio_set_direction(struct device *dev, unsigned int offset,
+int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
 			       int output);
 
 #endif

arch/sandbox/include/asm/io.h

@@ -40,4 +40,14 @@ static inline void unmap_sysmem(const void *vaddr)
 /* Map from a pointer to our RAM buffer */
 phys_addr_t map_to_sysmem(const void *ptr);
 
+/* Define nops for sandbox I/O access */
+#define readb(addr) 0
+#define readw(addr) 0
+#define readl(addr) 0
+#define writeb(v, addr)
+#define writew(v, addr)
+#define writel(v, addr)
+
+#include <iotrace.h>
+
 #endif

arch/sandbox/include/asm/system.h

@@ -8,10 +8,7 @@
 #define __ASM_SANDBOX_SYSTEM_H
 
 /* Define this as nops for sandbox architecture */
-static inline void local_irq_save(unsigned flags __attribute__((unused)))
-{
-}
-
+#define local_irq_save(x)
 #define local_irq_enable()
 #define local_irq_disable()
 #define local_save_flags(x)

arch/x86/config.mk

@@ -16,17 +16,18 @@ PF_CPPFLAGS_X86   := $(call cc-option, -fno-toplevel-reorder, \
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
 PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
+PLATFORM_CPPFLAGS += -march=i386 -m32
 
 # Support generic board on x86
 __HAVE_ARCH_GENERIC_BOARD := y
 
 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
 
-PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386
 
 LDFLAGS_FINAL += --gc-sections -pie
 LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
 
-export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+export NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
 CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib

arch/x86/cpu/config.mk

@@ -7,7 +7,7 @@
 
 CROSS_COMPILE ?= i386-linux-
 
-PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -Werror
 
 # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
 LDPPFLAGS += -DRESET_SEG_START=0xffff0000

arch/x86/dts/include/dt-bindings

@@ -0,0 +1 @@
+../../../../include/dt-bindings

board/Marvell/include/pci.h

@@ -7,8 +7,8 @@
 
 /* includes */
 
-#include"core.h"
-#include"memory.h"
+#include "core.h"
+#include "memory.h"
 
 /* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
 #define PCI_MAX_DEVICES 22

board/abilis/tb100/Makefile

@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= tb100.o

board/abilis/tb100/tb100.c

@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+#define CRM_SWRESET	0xff101044
+	writel(0x1, (void *)CRM_SWRESET);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
+		return 1;
+
+	return 0;
+}

board/adder/Makefile

@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= adder.o

board/adder/adder.c

@@ -1,108 +0,0 @@
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#if defined(CONFIG_OF_LIBFDT)
-	#include <libfdt.h>
-#endif
-
-/*
- * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
- *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
- * Minimal CPU frequency is 40MHz.
- */
-static uint sdram_table[] = {
-	/* Single read	(offset 0x00 in UPM RAM) */
-	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
-	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
-	/* Burst read	(offset 0x08 in UPM RAM) */
-	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
-	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
-	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
-	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
-	/* Single write (offset 0x18 in UPM RAM) */
-	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
-	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Burst write	(offset 0x20 in UPM RAM) */
-	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Refresh	(offset 0x30 in UPM RAM) */
-	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Exception	(offset 0x3C in UPM RAM) */
-	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
-};
-
-phys_size_t initdram (int board_type)
-{
-	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-	/* Configure SDRAM refresh */
-	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
-
-	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
-	udelay(200);
-
-	/* Run precharge from location 0x15 */
-	memctl->memc_mar = 0x0;
-	memctl->memc_mcr = 0x80002115;
-	udelay(200);
-
-	/* Run 8 refresh cycles */
-	memctl->memc_mcr = 0x80002830;
-	udelay(200);
-
-	/* Run MRS pattern from location 0x16 */
-	memctl->memc_mar = 0x88;
-	memctl->memc_mcr = 0x80002116;
-	udelay(200);
-
-	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
-
-	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
-	memctl->memc_or1  |= ~(msize - 1);
-
-	return msize;
-}
-
-int checkboard( void )
-{
-	puts("Board: Adder");
-#if defined(CONFIG_MPC885_FAMILY)
-	puts("87x\n");
-#elif defined(CONFIG_MPC866_FAMILY)
-	puts("II\n");
-#endif
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-}
-#endif

board/adder/u-boot.lds

@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text          :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
-ENTRY(_start)

board/ait/cam_enc_4xx/cam_enc_4xx.c

@@ -8,8 +8,8 @@
  */
 
 #include <common.h>
+#include <cli.h>
 #include <errno.h>
-#include <hush.h>
 #include <linux/mtd/nand.h>
 #include <nand.h>
 #include <miiphy.h>
@@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name)
 
 	sprintf(output, "%s old: %s value: ", name, getenv(name));
 	memset(cbuf, 0, CONFIG_SYS_CBSIZE);
-	readret = readline_into_buffer(output, cbuf, 0);
+	readret = cli_readline_into_buffer(output, cbuf, 0);
 
 	if (readret >= 0) {
 		ret = setenv(name, cbuf);

board/altera/common/sevenseg.c

@@ -1,204 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * common/sevenseg.c
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#include <common.h>
-#include <nios-io.h>
-
-#ifdef	CONFIG_SEVENSEG
-
-#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-#if (SEVENSEG_ACTIVE == 0)
-static unsigned int sevenseg_portval = ~0;
-#else
-static unsigned int sevenseg_portval = 0;
-#endif
-#endif
-
-static int sevenseg_init_done = 0;
-
-static inline void __sevenseg_set_masked (unsigned int mask, int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		sevenseg_portval &= ~mask;
-	else
-		sevenseg_portval |= mask;
-#else
-	if (value)
-		sevenseg_portval |= mask;
-	else
-		sevenseg_portval &= ~mask;
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		piop->data &= ~mask;
-	else
-		piop->data |= mask;
-#else
-	if (value)
-		piop->data |= mask;
-	else
-		piop->data &= ~mask;
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_toggle_masked (unsigned int mask)
-{
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-	sevenseg_portval ^= mask;
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-	piop->data ^= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_set (unsigned int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
-			 | ((~value)         & (~SEVENDEG_MASK_DP));
-#else
-	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
-			 | (value);
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	piop->data = (piop->data &   SEVENDEG_MASK_DP)
-		   | ((~value)   & (~SEVENDEG_MASK_DP));
-#else
-	piop->data = (piop->data & SEVENDEG_MASK_DP)
-		   | (value);
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_init (void)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-	__sevenseg_set(0);
-
-#ifndef	SEVENSEG_WRONLY	/* setup direction */
-
-	piop->direction |= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-
-void sevenseg_set(int value)
-{
-	unsigned char	digits[] = {
-		SEVENSEG_DIGITS_0,
-		SEVENSEG_DIGITS_1,
-		SEVENSEG_DIGITS_2,
-		SEVENSEG_DIGITS_3,
-		SEVENSEG_DIGITS_4,
-		SEVENSEG_DIGITS_5,
-		SEVENSEG_DIGITS_6,
-		SEVENSEG_DIGITS_7,
-		SEVENSEG_DIGITS_8,
-		SEVENSEG_DIGITS_9,
-		SEVENSEG_DIGITS_A,
-		SEVENSEG_DIGITS_B,
-		SEVENSEG_DIGITS_C,
-		SEVENSEG_DIGITS_D,
-		SEVENSEG_DIGITS_E,
-		SEVENSEG_DIGITS_F
-	};
-
-	if (!sevenseg_init_done) {
-		__sevenseg_init();
-		sevenseg_init_done++;
-	}
-
-	switch (value & SEVENSEG_MASK_CTRL) {
-
-		case SEVENSEG_RAW:
-			__sevenseg_set( (
-				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
-				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_OFF:
-			__sevenseg_set(0);
-			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPL:
-			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPH:
-			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_LO:
-		case SEVENSEG_HI:
-		case SEVENSEG_STR:
-		default:
-			break;
-	}
-}
-
-#endif	/* CONFIG_SEVENSEG */

board/altera/common/sevenseg.h

@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * common/sevenseg.h
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#ifndef __DK1S10_SEVENSEG_H__
-#define __DK1S10_SEVENSEG_H__
-
-#ifdef	CONFIG_SEVENSEG
-
-/*
- *  15                    8 7      0
- * |-----------------------|--------|
- * |   controll value      |  value |
- * ----------------------------------
- */
-#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
-#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
-#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
-#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
-#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
-#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
-#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
-#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
-#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
-#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
-#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
-
-#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
-#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
-
-#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
-
-#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	)
-#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-
-#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
-#error SEVENSEG: different pin asssignments not supported
-#endif
-
-void sevenseg_set(int value);
-
-#endif	/* CONFIG_SEVENSEG */
-
-#endif	/* __DK1S10_SEVENSEG_H__ */

board/altera/nios2-generic/Makefile

@@ -9,5 +9,4 @@
 obj-y	:= nios2-generic.o
 obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
 obj-$(CONFIG_EPLED) += ../common/epled.o
-obj-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
 obj-y	+= text_base.o

board/amcc/yucca/cmd_yucca.c

@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <cli.h>
 #include <command.h>
 #include "yucca.h"
 #include <i2c.h>
@@ -51,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 
 	do {
 		printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -74,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 			printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
 #endif
 		}
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -118,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 				printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
 
 #endif
-			nbytes = readline (" ? ");
+			nbytes = cli_readline(" ? ");
 
 			if (strcmp(console_buffer, "quit") == 0)
 				return 0;
@@ -142,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 
 	do {
 		printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -163,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 	printf("Pci-X clk = %s MHz\n", pcixClock);
 
 	do {
-		printf("\npress [y] to write I2C bootstrap \n");
-		printf("or [n] to abort.  \n");
-		printf("Don't forget to set board switches \n");
-		printf("according to your choice before re-starting \n");
-		printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+		printf("\npress [y] to write I2C bootstrap\n");
+		printf("or [n] to abort.\n");
+		printf("Don't forget to set board switches\n");
+		printf("according to your choice before re-starting\n");
+		printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
 
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 		if (strcmp(console_buffer, "n") == 0)
 			return 0;
 

board/astro/mcf5373l/fpga.c

@@ -100,7 +100,7 @@ int altera_done_fn(int cookie)
  * writing the complete buffer in one function is much faster,
  * then calling it for every bit
  */
-int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 {
 	size_t bytecount = 0;
 	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;

board/astro/mcf5373l/mcf5373l.c

@@ -79,7 +79,7 @@ phys_size_t initdram(int board_type)
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
 }
 

board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -133,20 +133,20 @@ static void at91sam9261ek_dm9000_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)

board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -111,20 +111,20 @@ static void at91sam9263ek_macb_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)

board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

@@ -121,20 +121,20 @@ static void at91sam9m10g45ek_macb_hw_init(void)
 #ifdef CONFIG_LCD
 
 vidinfo_t panel_info = {
-	vl_col:		480,
-	vl_row:		272,
-	vl_clk:		9000000,
-	vl_sync:	ATMEL_LCDC_INVLINE_NORMAL |
-			ATMEL_LCDC_INVFRAME_NORMAL,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	45,
-	vl_left_margin:	1,
-	vl_right_margin:1,
-	vl_vsync_len:	1,
-	vl_upper_margin:40,
-	vl_lower_margin:1,
-	mmio :		 ATMEL_BASE_LCDC,
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 

board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -78,20 +78,20 @@ static void at91sam9rlek_nand_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)

board/compulab/cm_t335/u-boot.lds

@@ -62,6 +62,8 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
+	.hash : { *(.hash*) }
+
 	.end :
 	{
 		*(.__end)
@@ -99,8 +101,6 @@ SECTIONS
 	}
 
 	.dynsym _image_binary_end : { *(.dynsym) }
-	.hash : { *(.hash) }
-	.got.plt : { *(.got.plt) }
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }

board/cray/L1/Makefile

@@ -15,13 +15,9 @@ quiet_cmd_awk = AWK     $@
 $(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
 	$(call cmd,awk)
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
 						-a 0 -e 0 -n bootscript
 $(obj)/bootscript.image: $(src)/bootscript.hush
 	$(call cmd,mkimage)
 
-clean-files := bootscript.c bootscript.image
+clean-files := bootscript.c bootscript.image

board/eltec/elppc/misc.c

@@ -7,6 +7,7 @@
 
 /* includes */
 #include <common.h>
+#include <cli.h>
 #include <linux/ctype.h>
 #include <pci.h>
 #include <net.h>
@@ -113,7 +114,7 @@ int misc_init_r (void)
 		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
 		printf ("  <r> to reenter revision info.\n");
 		printf ("=> ");
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			switch ((char) toupper (console_buffer[0])) {
 			case 'C':
 				copyNv = 1;
@@ -130,7 +131,7 @@ int misc_init_r (void)
 		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
 		printf ("Enter revision number (0-9): %c  ",
 			eerev.revision[0][0]);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			eerev.revision[0][0] =
 				(char) toupper (console_buffer[0]);
 			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
@@ -138,14 +139,14 @@ int misc_init_r (void)
 
 		printf ("Enter revision character (A-Z): %c  ",
 			eerev.revision[0][1]);
-		if (1 == readline (NULL)) {
+		if (1 == cli_readline(NULL)) {
 			eerev.revision[0][1] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter board name (V-XXXX-XXXX): %s  ",
 			(char *) &eerev.board);
-		if (11 == readline (NULL)) {
+		if (11 == cli_readline(NULL)) {
 			for (i = 0; i < 11; i++)
 				eerev.board[i] =
 					(char) toupper (console_buffer[i]);
@@ -153,14 +154,14 @@ int misc_init_r (void)
 		}
 
 		printf ("Enter serial number: %s ", (char *) &eerev.serial);
-		if (6 == readline (NULL)) {
+		if (6 == cli_readline(NULL)) {
 			for (i = 0; i < 6; i++)
 				eerev.serial[i] = console_buffer[i];
 			eerev.serial[6] = '\0';
 		}
 
 		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
-		if (12 == readline (NULL)) {
+		if (12 == cli_readline(NULL)) {
 			for (i = 0; i < 12; i += 2)
 				eerev.etheraddr[i >> 1] =
 					(char) (16 *
@@ -175,7 +176,7 @@ int misc_init_r (void)
 		l = strlen ((char *) &eerev.text);
 		printf ("Add to text section (max 64 chr): %s ",
 			(char *) &eerev.text);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			for (i = l; i < 63; i++)
 				eerev.text[i] = console_buffer[i - l];
 			eerev.text[63] = '\0';

board/eltec/mhpc/mhpc.c

@@ -14,6 +14,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <cli.h>
 #include <linux/ctype.h>
 #include <commproc.h>
 #include "mpc8xx.h"
@@ -146,21 +147,21 @@ int misc_init_r (void)
 	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
 		printf ("Enter revision number (0-9): %c  ",
 			mhpcRevInfo.revision[0]);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			mhpcRevInfo.revision[0] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter revision character (A-Z): %c  ",
 			mhpcRevInfo.revision[1]);
-		if (1 == readline (NULL)) {
+		if (1 == cli_readline(NULL)) {
 			mhpcRevInfo.revision[1] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter board name (V-XXXX-XXXX): %s  ",
 			(char *) &mhpcRevInfo.board);
-		if (11 == readline (NULL)) {
+		if (11 == cli_readline(NULL)) {
 			for (i = 0; i < 11; i++) {
 				mhpcRevInfo.board[i] =
 					(char) toupper (console_buffer[i]);
@@ -177,7 +178,7 @@ int misc_init_r (void)
 		do {
 			printf ("\nEnter sensor number (0-255): %d  ",
 				(int) mhpcRevInfo.sensor);
-			if (0 != readline (NULL)) {
+			if (0 != cli_readline(NULL)) {
 				mhpcRevInfo.sensor =
 					(unsigned char)
 					simple_strtoul (console_buffer, NULL,
@@ -187,7 +188,7 @@ int misc_init_r (void)
 
 		printf ("Enter serial number: %s ",
 			(char *) &mhpcRevInfo.serial);
-		if (6 == readline (NULL)) {
+		if (6 == cli_readline(NULL)) {
 			for (i = 0; i < 6; i++) {
 				mhpcRevInfo.serial[i] = console_buffer[i];
 			}
@@ -195,7 +196,7 @@ int misc_init_r (void)
 		}
 
 		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-		if (12 == readline (NULL)) {
+		if (12 == cli_readline(NULL)) {
 			for (i = 0; i < 12; i += 2) {
 				mhpcRevInfo.etheraddr[i >> 1] =
 					(char) (16 *

board/ep8248/Makefile

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ep8248.o

board/ep8248/ep8248.c

@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP8248 boards.
- * Tested on EP8248E.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
-	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
-	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
-	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
-	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
-	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
-	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
-	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
-	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
-    },
-
-    /* Port B */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
-	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
-	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
-	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
-	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
-	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
-	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
-	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
-	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
-    },
-
-    /* Port D */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
-	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
-	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
-	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
-	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
-	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
-	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
-	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
-	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
-	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
-	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
-	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
-	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
-	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
-	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
-	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
-	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
-	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
-	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
-	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
-	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
-	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
-	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
-	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
-	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
-	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
-	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
-	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    }
-};
-
-int board_early_init_f (void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	bcsr[4] |= 0x30; /* Turn the LEDs off */
-
-#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
-	bcsr[6] |= 0x10;
-#endif
-#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
-	bcsr[7] |= 0x10;
-#endif
-
-#if CONFIG_SYS_FCC1
-	bcsr[8] |= 0xC0;
-#endif /* CONFIG_SYS_FCC1 */
-#if CONFIG_SYS_FCC2
-	bcsr[8] |= 0x30;
-#endif /* CONFIG_SYS_FCC2 */
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-	long int msize = 16L << (bcsr[2] & 3);
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
-	uchar c = 0xFF;
-	uint psdmr = CONFIG_SYS_PSDMR;
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x02;
-	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
-	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
-	*ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/* Return total 60x bus SDRAM size */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	puts("Board: ");
-	switch (bcsr[0]) {
-	case 0x0C:
-		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
-		break;
-	default:
-		printf("unknown: ID=%02X\n", bcsr[0]);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

board/etin/debris/Makefile

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y =  debris.o flash.o phantom.o

board/etin/debris/debris.c

@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard (void)
-{
-	/*TODO: Check processor type */
-
-	puts (	"Board: Debris "
-#ifdef CONFIG_MPC8240
-		"8240"
-#endif
-#ifdef CONFIG_MPC8245
-		"8245"
-#endif
-		" ##Test not implemented yet##\n");
-	return 0;
-}
-
-#if 0	/* NOT USED */
-int checkflash (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("## Test not implemented yet ##\n");
-
-	return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
-	int m, row, col, bank, i;
-	unsigned long start, end;
-	uint32_t mccr1;
-	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
-	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
-	uint8_t mber = 0;
-
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
-	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
-	row = i2c_reg_read (0x50, 3);	/* # of rows */
-	col = i2c_reg_read (0x50, 4);	/* # of columns */
-	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
-
-	CONFIG_READ_WORD(MCCR1, mccr1);
-	mccr1 &= 0xffff0000;
-
-	start = CONFIG_SYS_SDRAM_BASE;
-	end = start + (1 << (col + row + 3) ) * bank - 1;
-
-	for (i = 0; i < m; i++) {
-		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
-		if (i < 4) {
-			msar1  |= ((start >> 20) & 0xff) << i * 8;
-			emsar1 |= ((start >> 28) & 0xff) << i * 8;
-			mear1  |= ((end >> 20) & 0xff) << i * 8;
-			emear1 |= ((end >> 28) & 0xff) << i * 8;
-		} else {
-			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
-			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
-			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
-			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
-		}
-		mber |= 1 << i;
-		start += (1 << (col + row + 3) ) * bank;
-		end += (1 << (col + row + 3) ) * bank;
-	}
-	for (; i < 8; i++) {
-		if (i < 4) {
-			msar1  |= 0xff << i * 8;
-			emsar1 |= 0x30 << i * 8;
-			mear1  |= 0xff << i * 8;
-			emear1 |= 0x30 << i * 8;
-		} else {
-			msar2  |= 0xff << (i-4) * 8;
-			emsar2 |= 0x30 << (i-4) * 8;
-			mear2  |= 0xff << (i-4) * 8;
-			emear2 |= 0x30 << (i-4) * 8;
-		}
-	}
-
-	CONFIG_WRITE_WORD(MCCR1, mccr1);
-	CONFIG_WRITE_WORD(MSAR1, msar1);
-	CONFIG_WRITE_WORD(EMSAR1, emsar1);
-	CONFIG_WRITE_WORD(MEAR1, mear1);
-	CONFIG_WRITE_WORD(EMEAR1, emear1);
-	CONFIG_WRITE_WORD(MSAR2, msar2);
-	CONFIG_WRITE_WORD(EMSAR2, emsar2);
-	CONFIG_WRITE_WORD(MEAR2, mear2);
-	CONFIG_WRITE_WORD(EMEAR2, emear2);
-	CONFIG_WRITE_BYTE(MBER, mber);
-
-	return (1 << (col + row + 3) ) * bank * m;
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_debris_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
-				       PCI_ENET1_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table: pci_debris_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*) dest;
-	volatile uchar *s = (volatile uchar*) src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-	return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*)dest;
-	volatile uchar *s = (volatile uchar*)src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-}
-
-int misc_init_r(void)
-{
-	uchar ethaddr[6];
-
-	if (eth_getenv_enetaddr("ethaddr", ethaddr))
-		/* Write ethernet addr in NVRAM for VxWorks */
-		nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
-				ethaddr, 6);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}

board/etin/debris/flash.c

@@ -1,705 +0,0 @@
-/*
- * board/eva/flash.c
- *
- * (C) Copyright 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <mpc824x.h>
-#include <asm/mmu.h>
-
-int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
-int (*write_dword)(flash_info_t*, ulong, uint64_t);
-
-typedef uint64_t cfi_word;
-
-#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
-
-#define cfi_write(flash, val, addr) \
-	move64((cfi_word*)&val, \
-			(cfi_word*)(flash->start[0] + addr))
-
-#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
-
-static void write32(unsigned long addr, uint32_t value)
-{
-	*(volatile uint32_t*)(addr) = value;
-	asm volatile("sync");
-}
-
-static uint32_t read32(unsigned long addr)
-{
-	uint32_t value;
-	value = *(volatile uint32_t*)addr;
-	asm volatile("sync");
-	return value;
-}
-
-static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
-{
-	uint32_t base = flash->start[0];
-	uint32_t val=(cmd << 16) | cmd;
-	addr <<= 3;
-	write32(base + addr, val);
-	return addr;
-}
-
-static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
-{
-	uint32_t base = flash->start[0];
-	addr <<= 3;
-	return (uint16_t)read32(base + addr);
-}
-
-flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static void move64(uint64_t *src, uint64_t *dest)
-{
-	asm volatile("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
-	 "stfd 0, 0(4)"         /* *dest  =  fpr0       */
-	 : : : "fr0" );         /* Clobbers fr0         */
-	return;
-}
-
-static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
-{
-	unsigned long start;
-	cfi_word status = 0;
-
-	status = cfi_read(flash, dest);
-	data &= status;
-
-	cfi_cmd(flash, 0x40, 0);
-	cfi_write(flash, data, dest);
-
-	udelay(10);
-	start = get_timer (0);
-	for(;;) {
-		status = cfi_read(flash, dest);
-		status &= CMD(0x80);
-		if(status == CMD(0x80))
-			break;
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			cfi_cmd(flash, 0xff, 0);
-			return 1;
-		}
-		udelay(1);
-	}
-	cfi_cmd(flash, 0xff, 0);
-
-	return 0;
-}
-
-static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
-{
-	ulong start;
-	cfi_word status = 0;
-
-	status = cfi_read(flash, dest);
-	if(status != CMD(0xffff)) return 2;
-
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	cfi_cmd(flash, 0xa0, 0x555);
-
-	cfi_write(flash, data, dest);
-
-	udelay(10);
-	start = get_timer (0);
-	status = ~data;
-	while(status != data) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-		status = cfi_read(flash, dest);
-		udelay(1);
-	}
-	return 0;
-}
-
-static __inline__ unsigned long get_msr(void)
-{
-	unsigned long msr;
-	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
-	return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
-}
-
-int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
-{
-	ulong wp;
-	int i, s, l, rc;
-	cfi_word data;
-	uint8_t *t = (uint8_t*)&data;
-	unsigned long base = flash->start[0];
-	uint32_t msr;
-
-	if (flash->flash_id == FLASH_UNKNOWN)
-		return 4;
-
-	if (cnt == 0)
-		return 0;
-
-	addr -= base;
-
-	msr = get_msr();
-	set_msr(msr|MSR_FP);
-
-	wp = (addr & ~7);   /* get lower word aligned address */
-
-	if((addr-wp) != 0) {
-		data = cfi_read(flash, wp);
-		s = addr & 7;
-		l = ( cnt < (8-s) ) ? cnt : (8-s);
-		for(i = 0; i < l; i++)
-			t[s+i] = *src++;
-		if ((rc = write_dword(flash, wp, data)) != 0)
-			goto DONE;
-		wp += 8;
-		cnt -= l;
-	}
-
-	while (cnt >= 8) {
-		for (i = 0; i < 8; i++)
-			t[i] = *src++;
-		if ((rc = write_dword(flash, wp, data)) != 0)
-			goto DONE;
-		wp  += 8;
-		cnt -= 8;
-	}
-
-	if (cnt == 0) {
-		rc = 0;
-		goto DONE;
-	}
-
-	data = cfi_read(flash, wp);
-	for(i = 0; i < cnt; i++)
-		t[i] = *src++;
-	rc = write_dword(flash, wp, data);
-DONE:
-	set_msr(msr);
-	return rc;
-}
-
-static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
-{
-	int sa;
-	int flag;
-	ulong start, last, now;
-	cfi_word status;
-
-	flag = disable_interrupts();
-
-	sa = (flash->start[sect] - flash->start[0]);
-	write32(flash->start[sect], 0x00200020);
-	write32(flash->start[sect], 0x00d000d0);
-
-	if (flag)
-		enable_interrupts();
-
-	udelay(1000);
-	start = get_timer (0);
-	last  = start;
-
-	for (;;) {
-		status = cfi_read(flash, sa);
-		status &= CMD(0x80);
-		if (status == CMD(0x80))
-			break;
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			cfi_cmd(flash, 0xff, 0);
-			printf ("Timeout\n");
-			return ERR_TIMOUT;
-		}
-
-		if ((now - last) > 1000) {
-			serial_putc ('.');
-			last = now;
-		}
-		udelay(10);
-	}
-	cfi_cmd(flash, 0xff, 0);
-	return ERR_OK;
-}
-
-static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
-	int sect;
-	int rc = ERR_OK;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (flash->protect[sect] == 0) {
-			rc = cfi_erase_oneblock(flash, sect);
-			if (rc != ERR_OK) break;
-		}
-	}
-	printf (" done\n");
-	return rc;
-}
-
-static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
-	int sect;
-	cfi_word status;
-	int sa = -1;
-	int flag;
-	ulong start, last, now;
-
-	flag = disable_interrupts();
-
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	cfi_cmd(flash, 0x80, 0x555);
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	for ( sect = s_first; sect <= s_last; sect++) {
-		if (flash->protect[sect] == 0) {
-			sa = flash->start[sect] - flash->start[0];
-			write32(flash->start[sect], 0x00300030);
-		}
-	}
-	if (flag)
-		enable_interrupts();
-
-	if (sa < 0)
-		goto DONE;
-
-	udelay (1000);
-	start = get_timer (0);
-	last  = start;
-	for(;;) {
-		status = cfi_read(flash, sa);
-		if (status == CMD(0xffff))
-			break;
-
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return ERR_TIMOUT;
-		}
-
-		if ((now - last) > 1000) {
-			serial_putc ('.');
-			last = now;
-		}
-		udelay(10);
-	}
-DONE:
-	cfi_cmd(flash, 0xf0, 0);
-
-	printf (" done\n");
-
-	return ERR_OK;
-}
-
-int flash_erase (flash_info_t *flash, int s_first, int s_last)
-{
-	int sect;
-	int prot;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (flash->flash_id == FLASH_UNKNOWN)
-			printf ("- missing\n");
-		else
-			printf ("- no sectors to erase\n");
-		return ERR_NOT_ERASED;
-	}
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return ERR_NOT_ERASED;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++)
-		if (flash->protect[sect]) prot++;
-
-	if (prot)
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-								prot);
-	else
-		printf ("\n");
-
-	return do_flash_erase(flash, s_first, s_last);
-}
-
-struct jedec_flash_info {
-	const uint16_t mfr_id;
-	const uint16_t dev_id;
-	const char *name;
-	const int DevSize;
-	const int InterfaceDesc;
-	const int NumEraseRegions;
-	const ulong regions[4];
-};
-
-#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
-
-#define SIZE_1MiB 20
-#define SIZE_2MiB 21
-#define SIZE_4MiB 22
-
-static const struct jedec_flash_info jedec_table[] = {
-	{
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV800T,
-		name: "AMD AM29LV800T",
-		DevSize: SIZE_1MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,15),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV800B,
-		name: "AMD AM29LV800B",
-		DevSize: SIZE_1MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,15),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV160T,
-		name: "AMD AM29LV160T",
-		DevSize: SIZE_2MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,31),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV160B,
-		name: "AMD AM29LV160B",
-		DevSize: SIZE_2MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x04000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x10000,31)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV320T,
-		name: "AMD AM29LV320T",
-		DevSize: SIZE_4MiB,
-		NumEraseRegions: 2,
-		regions: {ERASEINFO(0x10000,63),
-			  ERASEINFO(0x02000,8)
-		}
-
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV320B,
-		name: "AMD AM29LV320B",
-		DevSize: SIZE_4MiB,
-		NumEraseRegions: 2,
-		regions: {ERASEINFO(0x02000,8),
-			  ERASEINFO(0x10000,63)
-		}
-	}
-};
-
-static ulong cfi_init(uint32_t base,  flash_info_t *flash)
-{
-	int sector;
-	int block;
-	int block_count;
-	int offset = 0;
-	int reverse = 0;
-	int primary;
-	int mfr_id;
-	int dev_id;
-
-	flash->start[0] = base;
-	cfi_cmd(flash, 0xF0, 0);
-	cfi_cmd(flash, 0x98, 0);
-	if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
-		cfi_read_query(flash, 0x11) == 'R' &&
-		cfi_read_query(flash, 0x12) == 'Y' )) {
-		cfi_cmd(flash, 0xff, 0);
-		return 0;
-	}
-
-	flash->size = 1 << cfi_read_query(flash, 0x27);
-	flash->size *= 4;
-	block_count = cfi_read_query(flash, 0x2c);
-	primary = cfi_read_query(flash, 0x15);
-	if ( cfi_read_query(flash, primary + 4) == 0x30)
-		reverse = (cfi_read_query(flash, 0x1) & 0x01);
-	else
-		reverse = (cfi_read_query(flash, primary+15) == 3);
-
-	flash->sector_count = 0;
-
-	for ( block = reverse ? block_count - 1	: 0;
-		      reverse ? block >= 0	: block < block_count;
-		      reverse ? block--		: block ++) {
-		int sector_size =
-			(cfi_read_query(flash, 0x2d + block*4+2) |
-			(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
-		int sector_count =
-			(cfi_read_query(flash, 0x2d + block*4+0) |
-			(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
-		for(sector = 0; sector < sector_count; sector++) {
-			flash->start[flash->sector_count++] = base + offset;
-			offset += sector_size * 4;
-		}
-	}
-	mfr_id = cfi_read_query(flash, 0x00);
-	dev_id = cfi_read_query(flash, 0x01);
-
-	cfi_cmd(flash, 0xff, 0);
-
-	flash->flash_id = (mfr_id << 16) | dev_id;
-
-	for (sector = 0; sector < flash->sector_count; sector++) {
-		write32(flash->start[sector], 0x00600060);
-		write32(flash->start[sector], 0x00d000d0);
-	}
-	cfi_cmd(flash, 0xff, 0);
-
-	for (sector = 0; sector < flash->sector_count; sector++)
-		flash->protect[sector] = 0;
-
-	do_flash_erase = cfi_erase;
-	write_dword = cfi_write_dword;
-
-	return flash->size;
-}
-
-static ulong jedec_init(unsigned long base, flash_info_t *flash)
-{
-	int i;
-	int block, block_count;
-	int sector, offset;
-	int mfr_id, dev_id;
-	flash->start[0] = base;
-	cfi_cmd(flash, 0xF0, 0x000);
-	cfi_cmd(flash, 0xAA, 0x555);
-	cfi_cmd(flash, 0x55, 0x2AA);
-	cfi_cmd(flash, 0x90, 0x555);
-	mfr_id = cfi_read_query(flash, 0x000);
-	dev_id = cfi_read_query(flash, 0x0001);
-	cfi_cmd(flash, 0xf0, 0x000);
-
-	for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
-		if((jedec_table[i].mfr_id == mfr_id) &&
-			(jedec_table[i].dev_id == dev_id)) {
-
-			flash->flash_id = (mfr_id << 16) | dev_id;
-			flash->size = 1 << jedec_table[0].DevSize;
-			flash->size *= 4;
-			block_count = jedec_table[i].NumEraseRegions;
-			offset = 0;
-			flash->sector_count = 0;
-			for (block = 0; block < block_count; block++) {
-				int sector_size = jedec_table[i].regions[block];
-				int sector_count = (sector_size & 0xff) + 1;
-				sector_size >>= 8;
-				for (sector=0; sector<sector_count; sector++) {
-					flash->start[flash->sector_count++] =
-						base + offset;
-					offset += sector_size * 4;
-				}
-			}
-			break;
-		}
-	}
-
-	for (sector = 0; sector < flash->sector_count; sector++)
-		flash->protect[sector] = 0;
-
-	do_flash_erase = jedec_erase;
-	write_dword = jedec_write_dword;
-
-	return flash->size;
-}
-
-inline void mtibat1u(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   530, %0" :: "r" (x));
-}
-
-inline void mtibat1l(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   531, %0" :: "r" (x));
-}
-
-inline void mtdbat1u(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   538, %0" :: "r" (x));
-}
-
-inline void mtdbat1l(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   539, %0" :: "r" (x));
-}
-
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i;
-	unsigned int msr;
-
-	/* BAT1 */
-	CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
-	CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
-	msr = get_msr();
-	set_msr(msr & ~(MSR_IR | MSR_DR));
-	mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	set_msr(msr);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-	if (!size)
-		size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN)
-		printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-
-	return size;
-}
-
-void flash_print_info  (flash_info_t *flash)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *p;
-
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		flash_init();
-	}
-
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (((flash->flash_id) >> 16) & 0xff) {
-	case 0x01:
-		printf ("AMD ");
-		break;
-	case 0x04:
-		printf("FUJITSU ");
-		break;
-	case 0x20:
-		printf("STM ");
-		break;
-	case 0xBF:
-		printf("SST ");
-		break;
-	case 0x89:
-	case 0xB0:
-		printf("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch ((flash->flash_id) & 0xffff) {
-	case (uint16_t)AMD_ID_LV800T:
-		printf ("AM29LV800T\n");
-		break;
-	case (uint16_t)AMD_ID_LV800B:
-		printf ("AM29LV800B\n");
-		break;
-	case (uint16_t)AMD_ID_LV160T:
-		printf ("AM29LV160T\n");
-		break;
-	case (uint16_t)AMD_ID_LV160B:
-		printf ("AM29LV160B\n");
-		break;
-	case (uint16_t)AMD_ID_LV320T:
-		printf ("AM29LV320T\n");
-		break;
-	case (uint16_t)AMD_ID_LV320B:
-		printf ("AM29LV320B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F800C3T:
-		printf ("28F800C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F800C3B:
-		printf ("28F800C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F160C3T:
-		printf ("28F160C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F160C3B:
-		printf ("28F160C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F320C3T:
-		printf ("28F320C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F320C3B:
-		printf ("28F320C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F640C3T:
-		printf ("28F640C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F640C3B:
-		printf ("28F640C3B\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	if (flash->size >= (1 << 20)) {
-		printf ("  Size: %ld MB in %d Sectors\n",
-				flash->size >> 20, flash->sector_count);
-	} else {
-		printf ("  Size: %ld kB in %d Sectors\n",
-				flash->size >> 10, flash->sector_count);
-	}
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < flash->sector_count; ++i) {
-		/* Check if whole sector is erased*/
-		if (i != (flash->sector_count-1))
-			size = flash->start[i+1] - flash->start[i];
-		else
-			size = flash->start[0] + flash->size - flash->start[i];
-
-		erased = 1;
-		p = (volatile unsigned long *)flash->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++) {
-			if (*p++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-
-		printf (" %08lX%s%s",
-			flash->start[i],
-			erased ? " E" : "  ",
-			flash->protect[i] ? "RO " : "   ");
-	}
-	printf ("\n");
-}

board/etin/debris/phantom.c

@@ -1,301 +0,0 @@
-/*
- * board/eva/phantom.c
- *
- * Phantom RTC device driver for EVA
- *
- * Author: Sangmoon Kim
- *         dogoil@etinsys.com
- *
- * Copyright 2002 Etinsys Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
-
-#define RTC_YEAR                ( RTC_BASE + 7 )
-#define RTC_MONTH               ( RTC_BASE + 6 )
-#define RTC_DAY_OF_MONTH        ( RTC_BASE + 5 )
-#define RTC_DAY_OF_WEEK         ( RTC_BASE + 4 )
-#define RTC_HOURS               ( RTC_BASE + 3 )
-#define RTC_MINUTES             ( RTC_BASE + 2 )
-#define RTC_SECONDS             ( RTC_BASE + 1 )
-#define RTC_CENTURY             ( RTC_BASE + 0 )
-
-#define RTC_CONTROLA            RTC_CENTURY
-#define RTC_CONTROLB            RTC_SECONDS
-#define RTC_CONTROLC            RTC_DAY_OF_WEEK
-
-#define RTC_CA_WRITE            0x80
-#define RTC_CA_READ             0x40
-
-#define RTC_CB_OSC_DISABLE      0x80
-
-#define RTC_CC_BATTERY_FLAG     0x80
-#define RTC_CC_FREQ_TEST        0x40
-
-
-static int phantom_flag = -1;
-static int century_flag = -1;
-
-static uchar rtc_read(unsigned int addr)
-{
-	return *(volatile unsigned char *)(addr);
-}
-
-static void rtc_write(unsigned int addr, uchar val)
-{
-	*(volatile unsigned char *)(addr) = val;
-}
-
-static unsigned char phantom_rtc_sequence[] = {
-	0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
-};
-
-static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
-{
-	int i, j;
-	unsigned char v;
-	unsigned char save = rtc_read(addr);
-
-	for (j = 0; j < 8; j++) {
-		v = phantom_rtc_sequence[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	for (j = 0; j < 8; j++) {
-		v = 0;
-		for (i = 0; i < 8; i++) {
-			if(rtc_read(addr) & 1)
-				v |= 1 << i;
-		}
-		rtc[j] = v;
-	}
-	rtc_write(addr, save);
-	return rtc;
-}
-
-static void phantom_rtc_write(int addr, unsigned char rtc[8])
-{
-	int i, j;
-	unsigned char v;
-	unsigned char save = rtc_read(addr);
-	for (j = 0; j < 8; j++) {
-		v = phantom_rtc_sequence[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	for (j = 0; j < 8; j++) {
-		v = rtc[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	rtc_write(addr, save);
-}
-
-static int get_phantom_flag(void)
-{
-	int i;
-	unsigned char rtc[8];
-
-	phantom_rtc_read(RTC_BASE, rtc);
-
-	for(i = 1; i < 8; i++) {
-		if (rtc[i] != rtc[0])
-			return 1;
-	}
-	return 0;
-}
-
-void rtc_reset(void)
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag) {
-		unsigned char rtc[8];
-		phantom_rtc_read(RTC_BASE, rtc);
-		if(rtc[4] & 0x30) {
-			printf( "real-time-clock was stopped. Now starting...\n" );
-			rtc[4] &= 0x07;
-			phantom_rtc_write(RTC_BASE, rtc);
-		}
-	} else {
-		uchar reg_a, reg_b, reg_c;
-		reg_a = rtc_read( RTC_CONTROLA );
-		reg_b = rtc_read( RTC_CONTROLB );
-
-		if ( reg_b & RTC_CB_OSC_DISABLE )
-		{
-			printf( "real-time-clock was stopped. Now starting...\n" );
-			reg_a |= RTC_CA_WRITE;
-			reg_b &= ~RTC_CB_OSC_DISABLE;
-			rtc_write( RTC_CONTROLA, reg_a );
-			rtc_write( RTC_CONTROLB, reg_b );
-		}
-
-		/* make sure read/write clock register bits are cleared */
-		reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
-		rtc_write( RTC_CONTROLA, reg_a );
-
-		reg_c = rtc_read( RTC_CONTROLC );
-		if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
-			printf( "RTC battery low. Clock setting may not be reliable.\n");
-	}
-}
-
-static int get_century_flag(void)
-{
-	int flag = 0;
-	int bcd, century;
-	bcd = rtc_read( RTC_CENTURY );
-	century = bcd2bin( bcd & 0x3F );
-	rtc_write( RTC_CENTURY, bin2bcd(century+1));
-	if (bcd == rtc_read( RTC_CENTURY ))
-		flag = 1;
-	rtc_write( RTC_CENTURY, bcd);
-	return flag;
-}
-
-int rtc_get( struct rtc_time *tmp)
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag)
-	{
-		unsigned char rtc[8];
-
-		phantom_rtc_read(RTC_BASE, rtc);
-
-		tmp->tm_sec	= bcd2bin(rtc[1] & 0x7f);
-		tmp->tm_min	= bcd2bin(rtc[2] & 0x7f);
-		tmp->tm_hour	= bcd2bin(rtc[3] & 0x1f);
-		tmp->tm_wday	= bcd2bin(rtc[4] & 0x7);
-		tmp->tm_mday	= bcd2bin(rtc[5] & 0x3f);
-		tmp->tm_mon	= bcd2bin(rtc[6] & 0x1f);
-		tmp->tm_year	= bcd2bin(rtc[7]) + 1900;
-		tmp->tm_yday = 0;
-		tmp->tm_isdst = 0;
-
-		if( (rtc[3] & 0x80)  && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
-		if (tmp->tm_year < 1970) tmp->tm_year += 100;
-	} else {
-		uchar sec, min, hour;
-		uchar mday, wday, mon, year;
-
-		int century;
-
-		uchar reg_a;
-
-		if (century_flag < 0)
-			century_flag = get_century_flag();
-
-		reg_a = rtc_read( RTC_CONTROLA );
-		/* lock clock registers for read */
-		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
-		sec     = rtc_read( RTC_SECONDS );
-		min     = rtc_read( RTC_MINUTES );
-		hour    = rtc_read( RTC_HOURS );
-		mday    = rtc_read( RTC_DAY_OF_MONTH );
-		wday    = rtc_read( RTC_DAY_OF_WEEK );
-		mon     = rtc_read( RTC_MONTH );
-		year    = rtc_read( RTC_YEAR );
-		century = rtc_read( RTC_CENTURY );
-
-		/* unlock clock registers after read */
-		rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
-		tmp->tm_sec  = bcd2bin( sec  & 0x7F );
-		tmp->tm_min  = bcd2bin( min  & 0x7F );
-		tmp->tm_hour = bcd2bin( hour & 0x3F );
-		tmp->tm_mday = bcd2bin( mday & 0x3F );
-		tmp->tm_mon  = bcd2bin( mon & 0x1F );
-		tmp->tm_wday = bcd2bin( wday & 0x07 );
-
-		if (century_flag) {
-			tmp->tm_year = bcd2bin( year ) +
-				( bcd2bin( century & 0x3F ) * 100 );
-		} else {
-			tmp->tm_year = bcd2bin( year ) + 1900;
-			if (tmp->tm_year < 1970) tmp->tm_year += 100;
-		}
-
-		tmp->tm_yday = 0;
-		tmp->tm_isdst= 0;
-	}
-
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag) {
-		uint year;
-		unsigned char rtc[8];
-
-		year = tmp->tm_year;
-		year -= (year < 2000) ? 1900 : 2000;
-
-		rtc[0] = bin2bcd(0);
-		rtc[1] = bin2bcd(tmp->tm_sec);
-		rtc[2] = bin2bcd(tmp->tm_min);
-		rtc[3] = bin2bcd(tmp->tm_hour);
-		rtc[4] = bin2bcd(tmp->tm_wday);
-		rtc[5] = bin2bcd(tmp->tm_mday);
-		rtc[6] = bin2bcd(tmp->tm_mon);
-		rtc[7] = bin2bcd(year);
-
-		phantom_rtc_write(RTC_BASE, rtc);
-	} else {
-		uchar reg_a;
-		if (century_flag < 0)
-			century_flag = get_century_flag();
-
-		/* lock clock registers for write */
-		reg_a = rtc_read( RTC_CONTROLA );
-		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
-		rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
-		rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
-		rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
-		rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
-		rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
-		rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
-		/* break year up into century and year in century */
-		if (century_flag) {
-			rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
-			rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
-			reg_a &= 0xc0;
-			reg_a |= bin2bcd( tmp->tm_year / 100 );
-		} else {
-			rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
-				((tmp->tm_year < 2000) ? 1900 : 2000)));
-		}
-
-		/* unlock clock registers after read */
-		rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
-	}
-
-	return 0;
-}
-
-#endif

board/etin/kvme080/Makefile

@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= kvme080.o multiverse.o

board/etin/kvme080/kvme080.c

@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-int checkboard(void)
-{
-	puts ("Board: KVME080\n");
-	return 0;
-}
-
-unsigned long setdram(int m, int row, int col, int bank)
-{
-	int i;
-	unsigned long start, end;
-	uint32_t mccr1;
-	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
-	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
-	uint8_t mber = 0;
-
-	CONFIG_READ_WORD(MCCR1, mccr1);
-	mccr1 &= 0xffff0000;
-
-	start = CONFIG_SYS_SDRAM_BASE;
-	end = start + (1 << (col + row + 3) ) * bank - 1;
-
-	for (i = 0; i < m; i++) {
-		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
-		if (i < 4) {
-			msar1  |= ((start >> 20) & 0xff) << i * 8;
-			emsar1 |= ((start >> 28) & 0xff) << i * 8;
-			mear1  |= ((end >> 20) & 0xff) << i * 8;
-			emear1 |= ((end >> 28) & 0xff) << i * 8;
-		} else {
-			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
-			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
-			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
-			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
-		}
-		mber |= 1 << i;
-		start += (1 << (col + row + 3) ) * bank;
-		end += (1 << (col + row + 3) ) * bank;
-	}
-	for (; i < 8; i++) {
-		if (i < 4) {
-			msar1  |= 0xff << i * 8;
-			emsar1 |= 0x30 << i * 8;
-			mear1  |= 0xff << i * 8;
-			emear1 |= 0x30 << i * 8;
-		} else {
-			msar2  |= 0xff << (i-4) * 8;
-			emsar2 |= 0x30 << (i-4) * 8;
-			mear2  |= 0xff << (i-4) * 8;
-			emear2 |= 0x30 << (i-4) * 8;
-		}
-	}
-
-	CONFIG_WRITE_WORD(MCCR1, mccr1);
-	CONFIG_WRITE_WORD(MSAR1, msar1);
-	CONFIG_WRITE_WORD(EMSAR1, emsar1);
-	CONFIG_WRITE_WORD(MEAR1, mear1);
-	CONFIG_WRITE_WORD(EMEAR1, emear1);
-	CONFIG_WRITE_WORD(MSAR2, msar2);
-	CONFIG_WRITE_WORD(EMSAR2, emsar2);
-	CONFIG_WRITE_WORD(MEAR2, mear2);
-	CONFIG_WRITE_WORD(EMEAR2, emear2);
-	CONFIG_WRITE_BYTE(MBER, mber);
-
-	return (1 << (col + row + 3) ) * bank * m;
-}
-
-phys_size_t initdram(int board_type)
-{
-	unsigned int msr;
-	long int size = 0;
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
-	mtmsr(msr);
-
-	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
-		size = 0x20000000;	/* 512MB */
-	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
-		size = 0x04000000;	/* 64MB */
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
-	mtmsr(msr);
-
-	return size;
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-int board_early_init_f(void)
-{
-	*(volatile unsigned char *)(0xff080120) = 0xfb;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	unsigned int msr;
-
-	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
-	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
-	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtmsr(msr);
-
-	return 0;
-}
-
-extern int multiverse_init(void);
-
-int misc_init_r(void)
-{
-	multiverse_init();
-	return 0;
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*) dest;
-	volatile uchar *s = (volatile uchar*) src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-	return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*)dest;
-	volatile uchar *s = (volatile uchar*)src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}

board/etin/kvme080/multiverse.c

@@ -1,184 +0,0 @@
-/*
- * multiverse.c
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/compiler.h>
-
-#include "multiverse.h"
-
-static unsigned long vme_asi_addr;
-static unsigned long vme_iack_addr;
-static unsigned long pci_reg_addr;
-static unsigned long vme_reg_addr;
-
-int multiv_reset(unsigned long base)
-{
-	writeb(0x09, base + VME_SLAVE32_AM);
-	writeb(0x39, base + VME_SLAVE24_AM);
-	writeb(0x29, base + VME_SLAVE16_AM);
-	writeb(0x2f, base + VME_SLAVE_REG_AM);
-	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
-	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
-	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
-#ifdef A32_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
-				base + VME_SLAVE32_MASK);
-		writeb(0x01, base + VME_SLAVE32_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE32_MASK);
-		writeb(0x00, base + VME_SLAVE32_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE32_MASK);
-	writeb(0x00, base + VME_SLAVE32_EN);
-#endif
-#ifdef A24_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE24_MASK);
-		writeb(0x01, base + VME_SLAVE24_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE24_MASK);
-		writeb(0x00, base + VME_SLAVE24_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE24_MASK);
-	writeb(0x00, base + VME_SLAVE24_EN);
-#endif
-#ifdef A16_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
-				base + VME_SLAVE16_MASK);
-		writeb(0x01, base + VME_SLAVE16_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE16_MASK);
-		writeb(0x00, base + VME_SLAVE16_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE16_MASK);
-	writeb(0x00, base + VME_SLAVE16_EN);
-#endif
-#ifdef REG_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE_REG_MASK);
-		writeb(0x01, base + VME_SLAVE_REG_EN);
-	} else {
-		writeb(0xf8, base + VME_SLAVE_REG_MASK);
-	}
-#else
-	writeb(0xf8, base + VME_SLAVE_REG_MASK);
-#endif
-	writeb(0x09, base + VME_MASTER32_AM);
-	writeb(0x39, base + VME_MASTER24_AM);
-	writeb(0x29, base + VME_MASTER16_AM);
-	writeb(0x2f, base + VME_MASTER_REG_AM);
-	writel(0x00000000, base + VME_RMW_ADRS);
-	writeb(0x00, base + VME_IRQ);
-	writeb(0x00, base + VME_INT_EN);
-	writel(0x00000000, base + VME_IRQ1_REG);
-	writel(0x00000000, base + VME_IRQ2_REG);
-	writel(0x00000000, base + VME_IRQ3_REG);
-	writel(0x00000000, base + VME_IRQ4_REG);
-	writel(0x00000000, base + VME_IRQ5_REG);
-	writel(0x00000000, base + VME_IRQ6_REG);
-	writel(0x00000000, base + VME_IRQ7_REG);
-	return 0;
-}
-
-void multiv_auto_slot_id(unsigned long base)
-{
-	__maybe_unused unsigned int vector;
-	int slot_id = 1;
-	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
-		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
-		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
-		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
-				base + VME_CTRL);
-		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
-		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-			while (readb(base + VME_INT) & 0x04) {
-				vector = *(volatile unsigned int*)
-					(vme_iack_addr + VME_IACK2);
-				*(unsigned char*)(vme_asi_addr + 0x7ffff)
-					= (slot_id << 3) & 0xff;
-				slot_id ++;
-				if (slot_id > 31)
-					break;
-			}
-		}
-	}
-}
-
-int multiverse_init(void)
-{
-	int i;
-	pci_dev_t pdev;
-	unsigned int bar[6];
-
-	pdev = pci_find_device(0x1895, 0x0001, 0);
-
-	if (pdev == 0)
-		return -1;
-
-	for (i = 0; i < 6; i++)
-		pci_read_config_dword (pdev,
-				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
-
-	pci_reg_addr = bar[0];
-	vme_reg_addr = bar[1] + 0x00F00000;
-	vme_iack_addr = bar[1] + 0x00200000;
-	vme_asi_addr = bar[3];
-
-	pci_write_config_dword (pdev, PCI_COMMAND,
-		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-	writel(0xFF000000, pci_reg_addr + P_TA1);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
-	writel(0xf0000000, pci_reg_addr + P_TA2);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
-	writel(0xF1000000, pci_reg_addr + P_TA3);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
-	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
-	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
-
-	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
-	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
-	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
-
-	writel(0xF0000000, pci_reg_addr + W_BA2);
-	writel(0xFF000000, pci_reg_addr + W_AM2);
-	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
-
-	writel(0xFF000000, pci_reg_addr + W_BA3);
-	writel(0xFF000000, pci_reg_addr + W_AM3);
-	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
-
-	writel(0x00000001, pci_reg_addr + W_ERR_CS);
-	writel(0x00000001, pci_reg_addr + P_ERR_CS);
-
-	multiv_reset(vme_reg_addr);
-	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
-		vme_reg_addr + VME_CTRL);
-
-	multiv_auto_slot_id(vme_reg_addr);
-
-	return 0;
-}

board/etin/kvme080/multiverse.h

@@ -1,173 +0,0 @@
-/*
- * multiverse.h
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MULTIVERSE_H__
-#define __MULTIVERSE_H__
-
-#define VME_A32_MSTR_BUS	0x90000000
-#define VME_A32_MSTR_SIZE	0x01000000
-
-#define VME_A32_SLV_SIZE	0x01000000
-
-#define VME_A32_SLV_BUS		0x90000000
-#define VME_A24_SLV_BUS		0x00000000
-#define VME_A16_SLV_BUS		0x00000000
-
-#define VME_A32_SLV_LOCAL	0x00000000
-#define VME_A24_SLV_LOCAL	0x00000000
-#define VME_A16_SLV_LOCAL	0x00000000
-
-#define A32_SLV_WINDOW
-#undef	A24_SLV_WINDOW
-#undef	A16_SLV_WINDOW
-#undef	REG_SLV_WINDOW
-
-/* PCI Registers */
-
-#define P_IMG_CTRL0		0x100
-#define P_BA0			0x104
-#define P_AM0			0x108
-#define P_TA0			0x10C
-#define P_IMG_CTRL1		0x110
-#define P_BA1			0x114
-#define P_AM1			0x118
-#define P_TA1			0x11C
-#define P_IMG_CTRL2		0x120
-#define P_BA2			0x124
-#define P_AM2			0x128
-#define P_TA2			0x12C
-#define P_IMG_CTRL3		0x130
-#define P_BA3			0x134
-#define P_AM3			0x138
-#define P_TA3			0x13C
-#define P_IMG_CTRL4		0x140
-#define P_BA4			0x144
-#define P_AM4			0x148
-#define P_TA4			0x14C
-#define P_IMG_CTRL5		0x150
-#define P_BA5			0x154
-#define P_AM5			0x158
-#define P_TA5			0x15C
-#define P_ERR_CS		0x160
-#define P_ERR_ADDR		0x164
-#define P_ERR_DATA		0x168
-
-#define WB_CONF_SPC_BAR		0x180
-#define W_IMG_CTRL1		0x184
-#define W_BA1			0x188
-#define W_AM1			0x18C
-#define W_TA1			0x190
-#define W_IMG_CTRL2		0x194
-#define W_BA2			0x198
-#define W_AM2			0x19C
-#define W_TA2			0x1A0
-#define W_IMG_CTRL3		0x1A4
-#define W_BA3			0x1A8
-#define W_AM3			0x1AC
-#define W_TA3			0x1B0
-#define W_IMG_CTRL4		0x1B4
-#define W_BA4			0x1B8
-#define W_AM4			0x1BC
-#define W_TA4			0x1C0
-#define W_IMG_CTRL5		0x1C4
-#define W_BA5			0x1C8
-#define W_AM5			0x1CC
-#define W_TA5			0x1D0
-#define W_ERR_CS		0x1D4
-#define W_ERR_ADDR		0x1D8
-#define W_ERR_DATA		0x1DC
-#define CNF_ADDR		0x1E0
-#define CNF_DATA		0x1E4
-#define INT_ACK			0x1E8
-#define ICR			0x1EC
-#define ISR			0x1F0
-
-/* VME registers */
-
-#define VME_SLAVE32_AM		0x03
-#define VME_SLAVE24_AM		0x02
-#define VME_SLAVE16_AM		0x01
-#define VME_SLAVE_REG_AM	0x00
-#define VME_SLAVE32_A		0x07
-#define VME_SLAVE24_A		0x06
-#define VME_SLAVE16_A		0x05
-#define VME_SLAVE_REG_A		0x04
-#define VME_SLAVE32_MASK	0x0B
-#define VME_SLAVE24_MASK	0x0A
-#define VME_SLAVE16_MASK	0x09
-#define VME_SLAVE_REG_MASK	0x08
-#define VME_SLAVE32_EN		0x0F
-#define VME_SLAVE24_EN		0x0E
-#define VME_SLAVE16_EN		0x0D
-#define VME_SLAVE_REG_EN	0x0C
-#define VME_MASTER32_AM		0x13
-#define VME_MASTER24_AM		0x12
-#define VME_MASTER16_AM		0x11
-#define VME_MASTER_REG_AM	0x10
-#define VME_RMW_ADRS		0x14
-#define VME_MBOX		0x18
-#define VME_STATUS		0x1E
-#define VME_CTRL		0x1C
-#define VME_IRQ			0x20
-#define VME_INT_EN		0x21
-#define VME_INT			0x22
-#define VME_IRQ1_REG		0x24
-#define VME_IRQ2_REG		0x28
-#define VME_IRQ3_REG		0x2C
-#define VME_IRQ4_REG		0x30
-#define VME_IRQ5_REG		0x34
-#define VME_IRQ6_REG		0x38
-#define VME_IRQ7_REG		0x3C
-
-/* VME control register */
-
-#define VME_CTRL_BRDRST		0x01
-#define VME_CTRL_SYSRST		0x02
-#define VME_CTRL_RMW		0x04
-#define VME_CTRL_SHORT_D	0x08
-#define VME_CTRL_SYSFAIL	0x10
-#define VME_CTRL_VOWN		0x20
-#define VME_CTRL_A16_REG_MODE	0x40
-
-/* VME status register */
-
-#define VME_STATUS_SYSCON	0x01
-#define VME_STATUS_SYSFAIL	0x02
-#define VME_STATUS_ACFAIL	0x04
-#define VME_STATUS_SYSRST	0x08
-#define VME_STATUS_VOWN		0x10
-
-/* Interrupt types */
-
-#define LVL1			0x0002
-#define LVL2			0x0004
-#define LVL3			0x0008
-#define LVL4			0x0010
-#define LVL5			0x0020
-#define LVL6			0x0040
-#define LVL7			0x0080
-#define MULTIVERSE_INTI_INT	0x0100
-#define MULTIVERSE_WB_INT	0x0200
-#define MULTIVERSE_PCI_INT	0x0400
-
-/* interrupt acknowledge */
-
-#define VME_IACK1		0x04
-#define VME_IACK2		0x08
-#define VME_IACK3		0x0c
-#define VME_IACK4		0x10
-#define VME_IACK5		0x14
-#define VME_IACK6		0x18
-#define VME_IACK7		0x1c
-
-#endif /* __MULTIVERSE_H__ */