Merge git://git.denx.de/u-boot-net

board/freescale/ls1043aqds/eth.c

@@ -476,6 +476,7 @@ int board_eth_init(bd_t *bis)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4)

board/freescale/ls1046aqds/eth.c

@@ -397,6 +397,7 @@ int board_eth_init(bd_t *bis)
 			}
 			break;
 		case PHY_INTERFACE_MODE_RGMII:
+		case PHY_INTERFACE_MODE_RGMII_TXID:
 			if (i == FM1_DTSEC3)
 				mdio_mux[i] = EMI1_RGMII1;
 			else if (i == FM1_DTSEC4)

drivers/net/fsl_mcdmafec.c

@@ -391,7 +391,7 @@ static int fec_init(struct eth_device *dev, bd_t * bd)
 	/* Set Opcode/Pause Duration Register */
 	fecp->opd = 0x00010020;
 
-	/* Setup Buffers and Buffer Desriptors */
+	/* Setup Buffers and Buffer Descriptors */
 	info->rxIdx = 0;
 	info->txIdx = 0;
 

drivers/net/mcffec.c

@@ -465,7 +465,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
 	fecp->emrbr = PKT_MAXBLR_SIZE;
 
 	/*
-	 * Setup Buffers and Buffer Desriptors
+	 * Setup Buffers and Buffer Descriptors
 	 */
 	info->rxIdx = 0;
 	info->txIdx = 0;

drivers/net/mvneta.c

@@ -540,7 +540,7 @@ static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
 	u32 val;
 
 	/* Only 255 descriptors can be added at once ; Assume caller
-	 * process TX desriptors in quanta less than 256
+	 * process TX descriptors in quanta less than 256
 	 */
 	val = pend_desc;
 	mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);

drivers/net/phy/realtek.c

@@ -95,17 +95,21 @@ static int rtl8211f_config(struct phy_device *phydev)
 
 	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
 
-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
-		/* enable TXDLY */
-		phy_write(phydev, MDIO_DEVAD_NONE,
-			  MIIM_RTL8211F_PAGE_SELECT, 0xd08);
-		reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
+	phy_write(phydev, MDIO_DEVAD_NONE,
+		  MIIM_RTL8211F_PAGE_SELECT, 0xd08);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
+
+	/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 		reg |= MIIM_RTL8211F_TX_DELAY;
-		phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
-		/* restore to default page 0 */
-		phy_write(phydev, MDIO_DEVAD_NONE,
-			  MIIM_RTL8211F_PAGE_SELECT, 0x0);
-	}
+	else
+		reg &= ~MIIM_RTL8211F_TX_DELAY;
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
+	/* restore to default page 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE,
+		  MIIM_RTL8211F_PAGE_SELECT, 0x0);
 
 	/* Set green LED for Link, yellow LED for Active */
 	phy_write(phydev, MDIO_DEVAD_NONE,

net/nfs.h

@@ -36,16 +36,13 @@
 #define NFSERR_ISDIR    21
 #define NFSERR_INVAL    22
 
-/* Block size used for NFS read accesses.  A RPC reply packet (including  all
+/*
+ * Block size used for NFS read accesses.  A RPC reply packet (including  all
  * headers) must fit within a single Ethernet frame to avoid fragmentation.
- * However, if CONFIG_IP_DEFRAG is set, the config file may want to use a
- * bigger value. In any case, most NFS servers are optimized for a power of 2.
+ * However, if CONFIG_IP_DEFRAG is set, a bigger value could be used.  In any
+ * case, most NFS servers are optimized for a power of 2.
  */
-#ifdef CONFIG_NFS_READ_SIZE
-#define NFS_READ_SIZE CONFIG_NFS_READ_SIZE
-#else
-#define NFS_READ_SIZE 1024 /* biggest power of two that fits Ether frame */
-#endif
+#define NFS_READ_SIZE	1024	/* biggest power of two that fits Ether frame */
 
 /* Values for Accept State flag on RPC answers (See: rfc1831) */
 enum rpc_accept_stat {