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@@ -26,8 +26,8 @@ ENTRY(debug_ll_init)
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and r1, r1, #SG_REVISION_TYPE_MASK
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mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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-#define PH1_SLD3_UART_CLK 36864000
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+#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
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+#define UNIPHIER_SLD3_UART_CLK 36864000
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cmp r1, #0x25
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bne ph1_sld3_end
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@@ -42,13 +42,13 @@ ENTRY(debug_ll_init)
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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- ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_sld3_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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-#define PH1_LD4_UART_CLK 36864000
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+#if defined(CONFIG_ARCH_UNIPHIER_LD4)
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+#define UNIPHIER_LD4_UART_CLK 36864000
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cmp r1, #0x26
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bne ph1_ld4_end
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@@ -59,13 +59,13 @@ ph1_sld3_end:
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sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
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- ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_ld4_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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-#define PH1_PRO4_UART_CLK 73728000
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+#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
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+#define UNIPHIER_PRO4_UART_CLK 73728000
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cmp r1, #0x28
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bne ph1_pro4_end
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@@ -80,13 +80,13 @@ ph1_ld4_end:
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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- ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_pro4_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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-#define PH1_SLD8_UART_CLK 80000000
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+#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
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+#define UNIPHIER_SLD8_UART_CLK 80000000
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cmp r1, #0x29
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bne ph1_sld8_end
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@@ -97,13 +97,13 @@ ph1_pro4_end:
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sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
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- ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_sld8_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
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-#define PH1_PRO5_UART_CLK 73728000
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+#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
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+#define UNIPHIER_PRO5_UART_CLK 73728000
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cmp r1, #0x2A
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bne ph1_pro5_end
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@@ -121,13 +121,13 @@ ph1_sld8_end:
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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- ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_pro5_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
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-#define PROXSTREAM2_UART_CLK 88900000
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+#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
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+#define UNIPHIER_PXS2_UART_CLK 88900000
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cmp r1, #0x2E
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bne proxstream2_end
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@@ -146,13 +146,13 @@ ph1_pro5_end:
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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- ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
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b init_uart
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proxstream2_end:
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#endif
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-#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
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-#define PH1_LD6B_UART_CLK 88900000
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+#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
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+#define UNIPHIER_LD6B_UART_CLK 88900000
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cmp r1, #0x2F
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bne ph1_ld6b_end
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@@ -170,7 +170,7 @@ proxstream2_end:
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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- ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
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+ ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
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b init_uart
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ph1_ld6b_end:
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