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@@ -135,6 +135,16 @@ static void setup_spi(void)
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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+iomux_v3_cfg_t const pcie_pads[] = {
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+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
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+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
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+};
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+
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+static void setup_pcie(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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+}
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+
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iomux_v3_cfg_t const di0_pads[] = {
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MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
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MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
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@@ -454,6 +464,7 @@ int overwrite_console(void)
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_enet();
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+ setup_pcie();
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return cpu_eth_init(bis);
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}
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