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@@ -13,6 +13,8 @@
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#include <asm/arch/orion5x.h>
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#elif defined(CONFIG_KIRKWOOD)
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#include <asm/arch/soc.h>
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+#elif defined(CONFIG_ARMADA_XP)
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+#include <linux/mbus.h>
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#endif
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/* SATA port registers */
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@@ -89,6 +91,41 @@ struct mvsata_port_registers {
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#define MVSATA_STATUS_OK 0
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#define MVSATA_STATUS_TIMEOUT -1
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+/*
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+ * Registers for SATA MBUS memory windows
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+ */
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+
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+#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
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+#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
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+
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+/*
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+ * Initialize SATA memory windows for Armada XP
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+ */
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+
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+#ifdef CONFIG_ARMADA_XP
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+static void mvsata_ide_conf_mbus_windows(void)
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+{
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+ const struct mbus_dram_target_info *dram;
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+ int i;
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+
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+ dram = mvebu_mbus_dram_info();
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+
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+ /* Disable windows, Set Size/Base to 0 */
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+ for (i = 0; i < 4; i++) {
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+ writel(0, MVSATA_WIN_CONTROL(i));
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+ writel(0, MVSATA_WIN_BASE(i));
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+ }
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+
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+ for (i = 0; i < dram->num_cs; i++) {
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+ const struct mbus_dram_window *cs = dram->cs + i;
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+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
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+ (dram->mbus_dram_target_id << 4) | 1,
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+ MVSATA_WIN_CONTROL(i));
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+ writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
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+ }
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+}
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+#endif
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+
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/*
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* Initialize one MVSATAHC port: set SControl's IPM to "always active"
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* and DET to "reset", then wait for SStatus's DET to become "device and
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@@ -137,6 +174,10 @@ int ide_preinit(void)
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int ret = MVSATA_STATUS_TIMEOUT;
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int status;
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+#ifdef CONFIG_ARMADA_XP
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+ mvsata_ide_conf_mbus_windows();
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+#endif
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+
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/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
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#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
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status = mvsata_ide_initialize_port(
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