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@@ -430,7 +430,6 @@ static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
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zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
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writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->ier);
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- /* Start the transfer by enabling manual start bit */
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/* wait for completion */
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do {
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@@ -516,7 +515,7 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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priv->rx_buf = din;
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priv->len = bitlen / 8;
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- debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
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+ debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
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bus->seq, slave_plat->cs, bitlen, priv->len, flags);
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/*
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@@ -569,8 +568,7 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
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writel(confr, ®s->cr);
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priv->freq = speed;
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- debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
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- priv->regs, priv->freq);
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+ debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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@@ -593,7 +591,7 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
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writel(confr, ®s->cr);
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priv->mode = mode;
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- debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
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+ debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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