|
@@ -206,7 +206,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
|
|
|
.read_idle_ctrl = 0x00050000,
|
|
|
.zq_config = 0x50074BE4,
|
|
|
.temp_alert_config = 0x0,
|
|
|
- .emif_ddr_phy_ctlr_1 = 0x0E084008,
|
|
|
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
|
|
|
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
|
|
|
.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
|
|
|
.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
|