Merge git://www.denx.de/git/u-boot-imx

arch/arm/include/asm/arch-mx6/clock.h

@@ -80,4 +80,5 @@ void enable_thermal_clk(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 void select_ldb_di_clock_source(enum ldb_di_clock clk);
 void enable_eim_clk(unsigned char enable);
+int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 #endif /* __ASM_ARCH_CLOCK_H */

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -13,3 +13,6 @@
 
 #define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \
 				   USBPHY_PWD_RXPWDRX))
+
+int imx6_pcie_toggle_power(void);
+int imx6_pcie_toggle_reset(void);

arch/arm/include/asm/arch-mx7/crm_regs.h

@@ -2000,29 +2000,29 @@ struct mxc_ccm_anatop_reg {
 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
 
 
-#define CCM_GPR(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i))
-#define CCM_OBSERVE(i)		(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i))
-#define CCM_SCTRL(i)		(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i))
-#define CCM_CCGR(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i))
-#define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
-
-#define CCM_GPR_SET(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
-#define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
-#define CCM_SCTRL_SET(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
-#define CCM_CCGR_SET(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
-#define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
-
-#define CCM_GPR_CLR(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
-#define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
-#define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
-#define CCM_CCGR_CLR(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
-#define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
-
-#define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
-#define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
-#define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
-#define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
-#define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
+#define CCM_GPR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
+#define CCM_OBSERVE(i)		(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
+#define CCM_SCTRL(i)		(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
+#define CCM_CCGR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
+#define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
+
+#define CCM_GPR_SET(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
+#define CCM_SCTRL_SET(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
+#define CCM_CCGR_SET(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
+
+#define CCM_GPR_CLR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
+#define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
+#define CCM_CCGR_CLR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
+
+#define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
+#define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
+#define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
 
 #define HW_CCM_GPR_WR(i, v)		writel((v), CCM_GPR(i))
 #define HW_CCM_CCM_OBSERVE_WR(i, v)	writel((v), CCM_OBSERVE(i))
@@ -2055,6 +2055,11 @@ struct mxc_ccm_anatop_reg {
 #define HW_CCM_ROOT_TARGET_TOGGLE(i, v)	writel((v), CCM_ROOT_TARGET_TOGGLE(i))
 
 #define CCM_CLK_ON_MSK	0x03
+#define CCM_CLK_ON_N_N	0x00 /* Domain clocks not needed */
+#define CCM_CLK_ON_R_W	0x02 /* Domain clocks needed when in RUN and WAIT */
+
+/* CCGR Mapping */
+#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */
 
 #define CCM_ROOT_TGT_POST_DIV_SHIFT	0
 #define CCM_ROOT_TGT_PRE_DIV_SHIFT	15

arch/arm/include/asm/arch-mx7/imx-regs.h

@@ -268,6 +268,8 @@ struct src {
 #define SRC_M4RCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
 #define SRC_M4RCR_ENABLE_M4_OFFSET		3
 #define SRC_M4RCR_ENABLE_M4_MASK		(1 << 3)
+#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
+#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
 
 /* GPR0 Bit Fields */
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u

arch/arm/include/asm/arch-mx7/mx7-ddr.h

@@ -0,0 +1,155 @@
+/*
+ * DDR controller registers of the i.MX7 architecture
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX7_DDR_H__
+#define __ASM_ARCH_MX7_DDR_H__
+
+/* DDRC Registers (DDRC_IPS_BASE_ADDR) */
+struct ddrc {
+	u32 mstr;		/* 0x0000 */
+	u32 reserved1[0x18];
+	u32 rfshtmg;		/* 0x0064 */
+	u32 reserved2[0x1a];
+	u32 init0;		/* 0x00d0 */
+	u32 init1;		/* 0x00d4 */
+	u32 reserved3;
+	u32 init3;		/* 0x00dc */
+	u32 init4;		/* 0x00e0 */
+	u32 init5;		/* 0x00e4 */
+	u32 reserved4[0x03];
+	u32 rankctl;		/* 0x00f4 */
+	u32 reserved5[0x02];
+	u32 dramtmg0;		/* 0x0100 */
+	u32 dramtmg1;		/* 0x0104 */
+	u32 dramtmg2;		/* 0x0108 */
+	u32 dramtmg3;		/* 0x010c */
+	u32 dramtmg4;		/* 0x0110 */
+	u32 dramtmg5;		/* 0x0114 */
+	u32 reserved6[0x02];
+	u32 dramtmg8;		/* 0x0120 */
+	u32 reserved7[0x17];
+	u32 zqctl0;		/* 0x0180 */
+	u32 reserved8[0x03];
+	u32 dfitmg0;		/* 0x0190 */
+	u32 dfitmg1;		/* 0x0194 */
+	u32 reserved9[0x02];
+	u32 dfiupd0;		/* 0x01a0 */
+	u32 dfiupd1;		/* 0x01a4 */
+	u32 dfiupd2;		/* 0x01a8 */
+	u32 reserved10[0x15];
+	u32 addrmap0;		/* 0x0200 */
+	u32 addrmap1;		/* 0x0204 */
+	u32 addrmap2;		/* 0x0208 */
+	u32 addrmap3;		/* 0x020c */
+	u32 addrmap4;		/* 0x0210 */
+	u32 addrmap5;		/* 0x0214 */
+	u32 addrmap6;		/* 0x0218 */
+	u32 reserved12[0x09];
+	u32 odtcfg;		/* 0x0240 */
+	u32 odtmap;		/* 0x0244 */
+};
+
+/* DDRC_MSTR fields */
+#define MSTR_DATA_BUS_WIDTH_MASK	0x3 << 12
+#define MSTR_DATA_BUS_WIDTH_SHIFT	12
+#define MSTR_DATA_ACTIVE_RANKS_MASK	0xf << 24
+#define MSTR_DATA_ACTIVE_RANKS_SHIFT	24
+/* DDRC_ADDRMAP1 fields */
+#define ADDRMAP1_BANK_B0_MASK		0x1f << 0
+#define ADDRMAP1_BANK_B0_SHIFT		0
+#define ADDRMAP1_BANK_B1_MASK		0x1f << 8
+#define ADDRMAP1_BANK_B1_SHIFT		8
+#define ADDRMAP1_BANK_B2_MASK		0x1f << 16
+#define ADDRMAP1_BANK_B2_SHIFT		16
+/* DDRC_ADDRMAP2 fields */
+#define ADDRMAP2_COL_B2_MASK		0xF << 0
+#define ADDRMAP2_COL_B2_SHIFT		0
+#define ADDRMAP2_COL_B3_MASK		0xF << 8
+#define ADDRMAP2_COL_B3_SHIFT		8
+#define ADDRMAP2_COL_B4_MASK		0xF << 16
+#define ADDRMAP2_COL_B4_SHIFT		16
+#define ADDRMAP2_COL_B5_MASK		0xF << 24
+#define ADDRMAP2_COL_B5_SHIFT		24
+/* DDRC_ADDRMAP3 fields */
+#define ADDRMAP3_COL_B6_MASK		0xF << 0
+#define ADDRMAP3_COL_B6_SHIFT		0
+#define ADDRMAP3_COL_B7_MASK		0xF << 8
+#define ADDRMAP3_COL_B7_SHIFT		8
+#define ADDRMAP3_COL_B8_MASK		0xF << 16
+#define ADDRMAP3_COL_B8_SHIFT		16
+#define ADDRMAP3_COL_B9_MASK		0xF << 24
+#define ADDRMAP3_COL_B9_SHIFT		24
+/* DDRC_ADDRMAP4 fields */
+#define ADDRMAP4_COL_B10_MASK		0xF << 0
+#define ADDRMAP4_COL_B10_SHIFT		0
+#define ADDRMAP4_COL_B11_MASK		0xF << 8
+#define ADDRMAP4_COL_B11_SHIFT		8
+/* DDRC_ADDRMAP5 fields */
+#define ADDRMAP5_ROW_B0_MASK		0xF << 0
+#define ADDRMAP5_ROW_B0_SHIFT		0
+#define ADDRMAP5_ROW_B1_MASK		0xF << 8
+#define ADDRMAP5_ROW_B1_SHIFT		8
+#define ADDRMAP5_ROW_B2_10_MASK		0xF << 16
+#define ADDRMAP5_ROW_B2_10_SHIFT	16
+#define ADDRMAP5_ROW_B11_MASK		0xF << 24
+#define ADDRMAP5_ROW_B11_SHIFT		24
+/* DDRC_ADDRMAP6 fields */
+#define ADDRMAP6_ROW_B12_MASK		0xF << 0
+#define ADDRMAP6_ROW_B12_SHIFT		0
+#define ADDRMAP6_ROW_B13_MASK		0xF << 8
+#define ADDRMAP6_ROW_B13_SHIFT		8
+#define ADDRMAP6_ROW_B14_MASK		0xF << 16
+#define ADDRMAP6_ROW_B14_SHIFT		16
+#define ADDRMAP6_ROW_B15_MASK		0xF << 24
+#define ADDRMAP6_ROW_B15_SHIFT		24
+
+/* DDRC_MP Registers */
+#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
+struct ddrc_mp {
+	u32 reserved1[0x25];
+	u32 pctrl_0;		/* 0x0094 */
+};
+
+/* DDR_PHY registers */
+struct ddr_phy {
+	u32 phy_con0;		/* 0x0000 */
+	u32 phy_con1;		/* 0x0004 */
+	u32 reserved1[0x02];
+	u32 phy_con4;		/* 0x0010 */
+	u32 reserved2;
+	u32 offset_lp_con0;	/* 0x0018 */
+	u32 reserved3;
+	u32 offset_rd_con0;	/* 0x0020 */
+	u32 reserved4[0x03];
+	u32 offset_wr_con0;	/* 0x0030 */
+	u32 reserved5[0x07];
+	u32 cmd_sdll_con0;	/* 0x0050 */
+	u32 reserved6[0x12];
+	u32 drvds_con0;		/* 0x009c */
+	u32 reserved7[0x04];
+	u32 mdll_con0;		/* 0x00b0 */
+	u32 reserved8[0x03];
+	u32 zq_con0;		/* 0x00c0 */
+};
+
+#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)
+
+#define MX7_CAL_VAL_MAX 5
+/* Calibration parameters */
+struct mx7_calibration {
+	int num_val;			/* Number of calibration values */
+	u32 values[MX7_CAL_VAL_MAX];	/* calibration values */
+};
+
+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
+		  struct ddr_phy *ddr_phy_regs_val,
+		  struct mx7_calibration *calib_param);
+
+#endif	/*__ASM_ARCH_MX7_DDR_H__ */

arch/arm/include/asm/arch-mx7/sys_proto.h

@@ -7,3 +7,4 @@
 #include <asm/mach-imx/sys_proto.h>
 
 void set_wdog_reset(struct wdog_regs *wdog);
+enum boot_device get_boot_device(void);

arch/arm/include/asm/mach-imx/sys_proto.h

@@ -107,6 +107,8 @@ void init_aips(void);
 void init_src(void);
 void imx_set_wdog_powerdown(bool enable);
 
+int board_mmc_get_env_dev(int devno);
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()

arch/arm/mach-imx/cpu.c

@@ -25,7 +25,7 @@
 #include <fsl_esdhc.h>
 #endif
 
-#if defined(CONFIG_DISPLAY_CPUINFO)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
 static u32 reset_cause = -1;
 
 static char *get_reset_cause(void)
@@ -132,7 +132,7 @@ unsigned imx_ddr_size(void)
 }
 #endif
 
-#if defined(CONFIG_DISPLAY_CPUINFO)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
 
 const char *get_imx_type(u32 imxtype)
 {

arch/arm/mach-imx/mx6/Kconfig

@@ -129,6 +129,15 @@ config TARGET_COLIBRI_IMX6
 	select DM_SERIAL
 	select DM_THERMAL
 
+config TARGET_DHCOMIMX6
+	bool "dh_imx6"
+	select BOARD_LATE_INIT
+	select BOARD_EARLY_INIT_F
+	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
+	imply CMD_SPL
+
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
@@ -428,6 +437,7 @@ source "board/boundary/nitrogen6x/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/dhelectronics/dh_imx6/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/engicam/geam6ul/Kconfig"

arch/arm/mach-imx/mx6/clock.c

@@ -1220,6 +1220,20 @@ void enable_thermal_clk(void)
 	enable_pll3();
 }
 
+#ifdef CONFIG_MTD_NOR_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR6);
+	if (enable)
+		reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+	else
+		reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+	__raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
@@ -1262,6 +1276,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
  */
@@ -1463,20 +1478,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
-#ifdef CONFIG_MTD_NOR_FLASH
-void enable_eim_clk(unsigned char enable)
-{
-	u32 reg;
-
-	reg = __raw_readl(&imx_ccm->CCGR6);
-	if (enable)
-		reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
-	else
-		reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
-	__raw_writel(reg, &imx_ccm->CCGR6);
-}
-#endif
-
 /***************************************************/
 
 U_BOOT_CMD(
@@ -1484,3 +1485,4 @@ U_BOOT_CMD(
 	"display clocks",
 	""
 );
+#endif

arch/arm/mach-imx/mx6/soc.c

@@ -13,6 +13,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/dma.h>
 #include <asm/mach-imx/hab.h>

arch/arm/mach-imx/mx7/Kconfig

@@ -18,6 +18,13 @@ choice
 	prompt "MX7 board select"
 	optional
 
+config TARGET_CL_SOM_IMX7
+	bool "CL-SOM-iMX7"
+	select MX7D
+	select DM
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_MX7DSABRESD
 	bool "mx7dsabresd"
 	select BOARD_LATE_INIT
@@ -51,6 +58,7 @@ endchoice
 config SYS_SOC
 	default "mx7"
 
+source "board/compulab/cl-som-imx7/Kconfig"
 source "board/freescale/mx7dsabresd/Kconfig"
 source "board/technexion/pico-imx7d/Kconfig"
 source "board/toradex/colibri_imx7/Kconfig"

arch/arm/mach-imx/mx7/Makefile

@@ -5,7 +5,7 @@
 #
 #
 
-obj-y	:= soc.o clock.o clock_slice.o
+obj-y	:= soc.o clock.o clock_slice.o ddr.o
 
 ifdef CONFIG_ARMV7_PSCI
 obj-y  += psci-mx7.o psci.o

arch/arm/mach-imx/mx7/ddr.c

@@ -0,0 +1,201 @@
+/*
+ * DDR controller configuration for the i.MX7 architecture
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-ddr.h>
+#include <common.h>
+
+/*
+ * Routine: mx7_dram_cfg
+ * Description: DDR controller configuration
+ *
+ * @ddrc_regs_val: DDRC registers value
+ * @ddrc_mp_val: DDRC_MP registers value
+ * @ddr_phy_regs_val: DDR_PHY registers value
+ * @calib_param: calibration parameters
+ *
+ */
+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
+		  struct ddr_phy *ddr_phy_regs_val,
+		  struct mx7_calibration *calib_param)
+{
+	struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
+	struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
+	struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
+	struct ddr_phy *const ddr_phy_regs =
+		(struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int i;
+
+	/* Assert DDR Controller preset and DDR PHY reset */
+	writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
+
+	/* DDR controller configuration */
+	writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
+	writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
+	writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
+	writel(ddrc_regs_val->init1, &ddrc_regs->init1);
+	writel(ddrc_regs_val->init0, &ddrc_regs->init0);
+	writel(ddrc_regs_val->init3, &ddrc_regs->init3);
+	writel(ddrc_regs_val->init4, &ddrc_regs->init4);
+	writel(ddrc_regs_val->init5, &ddrc_regs->init5);
+	writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
+	writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
+	writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
+	writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
+	writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
+	writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
+	writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
+	writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
+	writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
+	writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
+	writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
+	writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
+	writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
+	writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
+	writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
+	writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
+	writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
+	writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
+	writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
+	writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
+	writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
+
+	/* De-assert DDR Controller preset and DDR PHY reset */
+	clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
+
+	/* PHY configuration */
+	writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
+	writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
+	writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
+	writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
+	writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
+	writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
+	writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
+	writel(ddr_phy_regs_val->cmd_sdll_con0 |
+	       DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
+	       &ddr_phy_regs->cmd_sdll_con0);
+	writel(ddr_phy_regs_val->cmd_sdll_con0 &
+	       ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
+	       &ddr_phy_regs->cmd_sdll_con0);
+	writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
+
+	/* calibration */
+	for (i = 0; i < calib_param->num_val; i++)
+		writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
+
+	/* Wake_up DDR PHY */
+	HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
+	writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
+	       IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
+	       &iomuxc_gpr_regs->gpr[8]);
+	HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
+}
+
+/*
+ * Routine: imx_ddr_size
+ * Description: extract the current DRAM size from the DDRC registers
+ *
+ * @return: DRAM size
+ */
+unsigned int imx_ddr_size(void)
+{
+	struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
+	u32 reg_val, field_val;
+	int bits = 0;/* Number of address bits */
+
+	/* Count data bus width bits */
+	reg_val = readl(&ddrc_regs->mstr);
+	field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
+	bits += 2 - field_val;
+	/* Count rank address bits */
+	field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
+	if (field_val > 1)
+		bits += field_val - 1;
+	/* Count column address bits */
+	bits += 2;/* Column address 0 and 1 are fixed mapped */
+	reg_val = readl(&ddrc_regs->addrmap2);
+	field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	reg_val = readl(&ddrc_regs->addrmap3);
+	field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	reg_val = readl(&ddrc_regs->addrmap4);
+	field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
+	if (field_val <= 7)
+		bits++;
+	/* Count row address bits */
+	reg_val = readl(&ddrc_regs->addrmap5);
+	field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
+	if (field_val <= 11)
+		bits += 9;
+	field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	reg_val = readl(&ddrc_regs->addrmap6);
+	field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
+	if (field_val <= 11)
+		bits++;
+	/* Count bank bits */
+	reg_val = readl(&ddrc_regs->addrmap1);
+	field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
+	if (field_val <= 30)
+		bits++;
+	field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
+	if (field_val <= 30)
+		bits++;
+	field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
+	if (field_val <= 29)
+		bits++;
+
+	return 1 << bits;
+}

arch/arm/mach-imx/spl.c

@@ -14,6 +14,7 @@
 #include <asm/spl.h>
 #include <spl.h>
 #include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <g_dnl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -96,6 +97,27 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
+#elif defined(CONFIG_MX7)
+/* Translate iMX7 boot device to the SPL boot device enumeration */
+u32 spl_boot_device(void)
+{
+	enum boot_device boot_device_spl = get_boot_device();
+
+	switch (boot_device_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case SPI_NOR_BOOT:
+		return BOOT_DEVICE_SPI;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+#endif /* CONFIG_MX6 || CONFIG_MX7 */
+
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 {
@@ -104,7 +126,6 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 	return 0;
 }
 #endif
-#endif
 
 #if defined(CONFIG_SPL_MMC_SUPPORT)
 /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */

board/advantech/dms-ba16/dms-ba16.c

@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <pwm.h>
 DECLARE_GLOBAL_DATA_PTR;
 

board/aristainetos/aristainetos.c

@@ -28,6 +28,7 @@
 #include <asm/arch/crm_regs.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
+#include <input.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <pwm.h>

board/beckhoff/mx53cx9020/mx53cx9020.c

@@ -26,6 +26,7 @@
 #include <asm/gpio.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
+#include <input.h>
 #include <fs.h>
 #include <dm/platform_data/serial_mxc.h>
 

board/ccv/xpress/xpress.c

@@ -108,6 +108,8 @@ int dram_init(void)
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const uart4_pads[] = {
@@ -122,11 +124,14 @@ static iomux_v3_cfg_t const uart5_pads[] = {
 	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const uart7_pads[] = {
+	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const uart8_pads[] = {
-	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__UART8_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__UART8_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -134,6 +139,7 @@ static void setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+	imx_iomux_v3_setup_multiple_pads(uart7_pads, ARRAY_SIZE(uart7_pads));
 	imx_iomux_v3_setup_multiple_pads(uart8_pads, ARRAY_SIZE(uart8_pads));
 }
 

board/compulab/cl-som-imx7/Kconfig

@@ -0,0 +1,28 @@
+if TARGET_CL_SOM_IMX7
+
+config SYS_BOARD
+	default "cl-som-imx7"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "cl-som-imx7"
+
+config SYS_MMC_DEV
+	int
+	default 0
+
+config SYS_USB_DEV
+	int
+	default 0
+
+config SYS_MMC_IMG_LOAD_PART
+	int
+	default 1
+
+config SYS_USB_IMG_LOAD_PART
+	int
+	default 1
+
+endif

board/compulab/cl-som-imx7/MAINTAINERS

@@ -0,0 +1,6 @@
+CL-SOM-IMX7 BOARD
+M:	Uri Mashiach <uri.mashiach@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cl-som-imx7
+F:	include/configs/cl-som-imx7.h
+F:	configs/cl-som-imx7_defconfig

board/compulab/cl-som-imx7/Makefile

@@ -0,0 +1,17 @@
+#
+# Makefile
+#
+# (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+#
+# Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y := mux.o common.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y  += spl.o
+else
+obj-y  += cl-som-imx7.o
+endif

board/compulab/cl-som-imx7/cl-som-imx7.c

@@ -0,0 +1,331 @@
+/*
+ * U-Boot board functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <phy.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+#include <asm/arch-mx7/sys_proto.h>
+#include <asm/arch-mx7/clock.h>
+#include "../common/eeprom.h"
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SYS_I2C_MXC
+
+#define I2C_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+				PAD_CTL_HYS)
+
+#define CL_SOM_IMX7_GPIO_I2C2_SCL	IMX_GPIO_NR(1, 6)
+#define CL_SOM_IMX7_GPIO_I2C2_SDA	IMX_GPIO_NR(1, 7)
+
+static struct i2c_pads_info cl_som_imx7_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = CL_SOM_IMX7_GPIO_I2C2_SCL,
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 |
+			MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = CL_SOM_IMX7_GPIO_I2C2_SDA,
+	},
+};
+
+/*
+ * cl_som_imx7_setup_i2c() - I2C  pinmux configuration.
+ */
+static void cl_som_imx7_setup_i2c(void)
+{
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &cl_som_imx7_i2c_pad_info2);
+}
+#else /* !CONFIG_SYS_I2C_MXC */
+static void cl_som_imx7_setup_i2c(void) {}
+#endif /* CONFIG_SYS_I2C_MXC */
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define CL_SOM_IMX7_GPIO_USDHC3_PWR	IMX_GPIO_NR(6, 11)
+
+static struct fsl_esdhc_cfg cl_som_imx7_usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc2                    USDHC3 (eMMC)
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			cl_som_imx7_usdhc1_pads_set();
+			gpio_request(CL_SOM_IMX7_GPIO_USDHC1_CD, "usdhc1_cd");
+			cl_som_imx7_usdhc_cfg[0].sdhc_clk =
+				mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			cl_som_imx7_usdhc3_emmc_pads_set();
+			gpio_request(CL_SOM_IMX7_GPIO_USDHC3_PWR, "usdhc3_pwr");
+			gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 0);
+			udelay(500);
+			gpio_direction_output(CL_SOM_IMX7_GPIO_USDHC3_PWR, 1);
+			cl_som_imx7_usdhc_cfg[1].sdhc_clk =
+				mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers "
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &cl_som_imx7_usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_FEC_MXC
+
+#define CL_SOM_IMX7_ETH1_PHY_NRST	IMX_GPIO_NR(1, 4)
+
+/*
+ * cl_som_imx7_rgmii_rework() - Ethernet PHY configuration.
+ */
+static void cl_som_imx7_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= ~(0x1 << 8);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	cl_som_imx7_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * cl_som_imx7_handle_mac_address() - set Ethernet MAC address environment.
+ *
+ * @env_var: MAC address environment variable
+ * @eeprom_bus: I2C bus of the environment EEPROM
+ *
+ * @return: 0 on success, < 0 on failure
+ */
+static int cl_som_imx7_handle_mac_address(char *env_var, uint eeprom_bus)
+{
+	int ret;
+	unsigned char enetaddr[6];
+
+	ret = eth_env_get_enetaddr(env_var, enetaddr);
+	if (ret)
+		return 0;
+
+	ret = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
+	if (ret)
+		return ret;
+
+	ret = is_valid_ethaddr(enetaddr);
+	if (!ret)
+		return -1;
+
+	return eth_env_set_enetaddr(env_var, enetaddr);
+}
+
+#define CL_SOM_IMX7_FEC_DEV_ID_PRI 0
+
+int board_eth_init(bd_t *bis)
+{
+	/* set Ethernet MAC address environment */
+	cl_som_imx7_handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS);
+	/* Ethernet interface pinmux configuration  */
+	cl_som_imx7_phy1_rst_pads_set();
+	cl_som_imx7_fec1_pads_set();
+	/* PHY reset */
+	gpio_request(CL_SOM_IMX7_ETH1_PHY_NRST, "eth1_phy_nrst");
+	gpio_direction_output(CL_SOM_IMX7_ETH1_PHY_NRST, 0);
+	mdelay(10);
+	gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1);
+	/* MAC initialization */
+	return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI,
+				       CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+}
+
+/*
+ * cl_som_imx7_setup_fec() - Ethernet MAC 1 clock configuration.
+ * - ENET1 reference clock mode select.
+ * - ENET1_TX_CLK output driver is disabled when configured for ALT1.
+ */
+static void cl_som_imx7_setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	set_clk_enet(ENET_125MHZ);
+}
+#else /* !CONFIG_FEC_MXC */
+static void cl_som_imx7_setup_fec(void) {}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_SPI
+
+static void cl_som_imx7_spi_init(void)
+{
+	cl_som_imx7_espi1_pads_set();
+}
+#else /* !CONFIG_SPI */
+static void cl_som_imx7_spi_init(void) {}
+#endif /* CONFIG_SPI */
+
+int board_early_init_f(void)
+{
+	cl_som_imx7_uart1_pads_set();
+	cl_som_imx7_usb_otg1_pads_set();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	cl_som_imx7_setup_i2c();
+	cl_som_imx7_setup_fec();
+	cl_som_imx7_spi_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
+
+	return 0;
+}
+#endif /* CONFIG_POWER */
+
+/*
+ * cl_som_imx7_setup_wdog() - watchdog configuration.
+ * - Output WDOG_B signal to reset external pmic.
+ * - Suspend the watchdog timer during low-power modes.
+ */
+void cl_som_imx7_setup_wdog(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	cl_som_imx7_wdog_pads_set();
+	set_wdog_reset(wdog);
+       /*
+	* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	* since we use PMIC_PWRON to reset the board.
+	*/
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+}
+
+int board_late_init(void)
+{
+	env_set("board_name", "CL-SOM-iMX7");
+	cl_som_imx7_setup_wdog();
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *mode;
+
+	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
+		mode = "secure";
+	else
+		mode = "non-secure";
+
+	printf("Board: CL-SOM-iMX7 in %s mode\n", mode);
+
+	return 0;
+}

board/compulab/cl-som-imx7/common.c

@@ -0,0 +1,46 @@
+/*
+ * SPL/U-Boot common functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <asm-generic/gpio.h>
+#include "common.h"
+
+#ifdef CONFIG_SPI
+
+#define CL_SOM_IMX7_GPIO_SPI_CS	IMX_GPIO_NR(4, 19)
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	return CL_SOM_IMX7_GPIO_SPI_CS;
+}
+
+#endif /* CONFIG_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(CL_SOM_IMX7_GPIO_USDHC1_CD);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = 1; /* Assume uSDHC3 emmc is always present */
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC */

board/compulab/cl-som-imx7/common.h

@@ -0,0 +1,32 @@
+/*
+ * SPL/U-Boot common header file for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
+
+#ifdef CONFIG_FSL_ESDHC
+#define CL_SOM_IMX7_GPIO_USDHC1_CD	IMX_GPIO_NR(5, 0)
+PADS_SET_PROT(usdhc1_pads);
+#endif /* CONFIG_FSL_ESDHC */
+PADS_SET_PROT(uart1_pads);
+#ifdef CONFIG_SPI
+PADS_SET_PROT(espi1_pads);
+#endif /* CONFIG_SPI */
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_FSL_ESDHC
+PADS_SET_PROT(usdhc3_emmc_pads);
+#endif /* CONFIG_FSL_ESDHC */
+#ifdef CONFIG_FEC_MXC
+PADS_SET_PROT(phy1_rst_pads);
+PADS_SET_PROT(fec1_pads);
+#endif /* CONFIG_FEC_MXC */
+PADS_SET_PROT(usb_otg1_pads);
+PADS_SET_PROT(wdog_pads);
+#endif /* !CONFIG_SPL_BUILD */

board/compulab/cl-som-imx7/mux.c

@@ -0,0 +1,142 @@
+/*
+ * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+
+#define PADS_SET(pads_array)						       \
+void cl_som_imx7_##pads_array##_set(void)				       \
+{									       \
+	imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array));  \
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+				PAD_CTL_HYS | PAD_CTL_PUE | \
+				PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+PADS_SET(usdhc1_pads)
+
+#endif /* CONFIG_FSL_ESDHC */
+
+#define UART_PAD_CTRL		(PAD_CTL_DSE_3P3V_49OHM | \
+				PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+PADS_SET(uart1_pads)
+
+#ifdef CONFIG_SPI
+
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \
+			PAD_CTL_DSE_3P3V_32OHM)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
+			PAD_CTL_SRE_SLOW)
+
+static iomux_v3_cfg_t const espi1_pads[] = {
+	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+PADS_SET(espi1_pads)
+
+#endif /* CONFIG_SPI */
+
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_FSL_ESDHC
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+PADS_SET(usdhc3_emmc_pads)
+
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_FEC_MXC
+
+#define ENET_PAD_CTRL		(PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII	(PAD_CTL_PUS_PU5KOHM)
+
+static iomux_v3_cfg_t const phy1_rst_pads[] = {
+	/* PHY1 RST */
+	MX7D_PAD_GPIO1_IO04__GPIO1_IO4	| MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+PADS_SET(phy1_rst_pads)
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
+	MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
+	MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+};
+
+PADS_SET(fec1_pads)
+
+#endif /* CONFIG_FEC_MXC */
+
+static iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+PADS_SET(usb_otg1_pads)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+PADS_SET(wdog_pads)
+
+#endif /* !CONFIG_SPL_BUILD */

board/compulab/cl-som-imx7/spl.c

@@ -0,0 +1,211 @@
+/*
+ * SPL board functions for CompuLab CL-SOM-iMX7 module
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch-mx7/mx7-pins.h>
+#include <asm/arch-mx7/clock.h>
+#include <asm/arch-mx7/mx7-ddr.h>
+#include "common.h"
+
+#ifdef CONFIG_FSL_ESDHC
+
+static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
+	USDHC1_BASE_ADDR, 0, 4};
+
+int board_mmc_init(bd_t *bis)
+{
+	cl_som_imx7_usdhc1_pads_set();
+	cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static iomux_v3_cfg_t const led_pads[] = {
+	MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
+		PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
+};
+
+static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
+	.init1		= 0x00690000,
+	.init0		= 0x00020083,
+	.init3		= 0x09300004,
+	.init4		= 0x04080000,
+	.init5		= 0x00100004,
+	.rankctl	= 0x0000033F,
+	.dramtmg1	= 0x0007020E,
+	.dramtmg2	= 0x03040407,
+	.dramtmg3	= 0x00002006,
+	.dramtmg4	= 0x04020305,
+	.dramtmg5	= 0x03030202,
+	.dramtmg8	= 0x00000803,
+	.zqctl0		= 0x00810021,
+	.dfitmg0	= 0x02098204,
+	.dfitmg1	= 0x00030303,
+	.dfiupd0	= 0x80400003,
+	.dfiupd1	= 0x00100020,
+	.dfiupd2	= 0x80100004,
+	.addrmap4	= 0x00000F0F,
+	.odtcfg		= 0x06000604,
+	.odtmap		= 0x00000001,
+};
+
+static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {
+	.pctrl_0	= 0x00000001,
+};
+
+static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
+	.phy_con0	= 0x17420F40,
+	.phy_con1	= 0x10210100,
+	.phy_con4	= 0x00060807,
+	.mdll_con0	= 0x1010007E,
+	.drvds_con0	= 0x00000D6E,
+	.cmd_sdll_con0	= 0x00000010,
+	.offset_lp_con0	= 0x0000000F,
+};
+
+struct mx7_calibration cl_som_imx7_spl_calib_param = {
+	.num_val	= 5,
+	.values		= {
+		0x0E407304,
+		0x0E447304,
+		0x0E447306,
+		0x0E447304,
+		0x0E407304,
+	},
+};
+
+static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)
+{
+	switch (ram_size) {
+	case SZ_256M:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01041001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000014;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00151515;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x03030303;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0303;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	case SZ_512M:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000015;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00161616;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F0F0404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0C0C0C0C;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	case SZ_1G:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x00400046;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E1109;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000016;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00171717;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x0F040404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x02020202;
+		break;
+	case SZ_2G:
+		cl_som_imx7_spl_ddrc_regs_val.mstr		= 0x01040001;
+		cl_som_imx7_spl_ddrc_regs_val.rfshtmg		= 0x0040005E;
+		cl_som_imx7_spl_ddrc_regs_val.dramtmg0		= 0x090E110A;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap0		= 0x00000018;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap1		= 0x00181818;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap5		= 0x04040404;
+		cl_som_imx7_spl_ddrc_regs_val.addrmap6		= 0x04040404;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0	= 0x0A0A0A0A;
+		cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0	= 0x04040404;
+		break;
+	}
+
+	mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,
+		     &cl_som_imx7_spl_ddrc_mp_val,
+		     &cl_som_imx7_spl_ddr_phy_regs_val,
+		     &cl_som_imx7_spl_calib_param);
+}
+
+static void cl_som_imx7_spl_dram_cfg(void)
+{
+	ulong ram_size_test, ram_size = 0;
+
+	for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {
+		cl_som_imx7_spl_dram_cfg_size(ram_size);
+		ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
+		if (ram_size_test == ram_size)
+			break;
+	}
+
+	if (ram_size < SZ_256M) {
+		puts("!!!ERROR!!! DRAM detection failed!!!\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+
+static void cl_som_imx7_spl_spi_init(void)
+{
+	cl_som_imx7_espi1_pads_set();
+}
+#else /* !CONFIG_SPL_SPI_SUPPORT */
+static void cl_som_imx7_spl_spi_init(void) {}
+#endif /* CONFIG_SPL_SPI_SUPPORT */
+
+void board_init_f(ulong dummy)
+{
+	imx_iomux_v3_setup_multiple_pads(led_pads, 1);
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+	/* setup GP timer */
+	timer_init();
+	cl_som_imx7_spl_spi_init();
+	cl_som_imx7_uart1_pads_set();
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+	/* DRAM detection  */
+	cl_som_imx7_spl_dram_cfg();
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+	u32 boot_device = spl_boot_device();
+
+	if (boot_device == BOOT_DEVICE_SPI)
+		puts("Booting from SPI flash\n");
+	else if (boot_device == BOOT_DEVICE_MMC1)
+		puts("Booting from SD card\n");
+	else
+		puts("Unknown boot device\n");
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_SPI:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+		break;
+	}
+}

board/congatec/cgtqmx6eval/cgtqmx6eval.c

@@ -24,6 +24,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
+#include <input.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include <linux/fb.h>
@@ -683,8 +684,6 @@ int overwrite_console(void)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-	setup_display();
-
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
@@ -702,6 +701,8 @@ int board_init(void)
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 
+	setup_display();
+
 #ifdef CONFIG_SATA
 	setup_sata();
 #endif

board/dhelectronics/dh_imx6/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_DHCOMIMX6
+
+config SYS_BOARD
+	default "dh_imx6"
+
+config SYS_VENDOR
+	default "dhelectronics"
+
+config SYS_CONFIG_NAME
+	default "dh_imx6"
+
+endif

board/dhelectronics/dh_imx6/MAINTAINERS

@@ -0,0 +1,7 @@
+DH_IMX6 BOARD
+M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>, Ludwig Zenz <lzenz@dh-electronics.de>
+S:	Maintained
+F:	board/dhelectronics/dh_imx6/
+F:	include/configs/dh_imx6.h
+F:	configs/dh_mx6q_defconfig
+F:	configs/dh_mx6dl_defconfig

board/dhelectronics/dh_imx6/Makefile

@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= dh_imx6_spl.o
+else
+obj-y	:= dh_imx6.o
+endif

board/dhelectronics/dh_imx6/dh_imx6.c

@@ -0,0 +1,437 @@
+/*
+ * DHCOM DH-iMX6 PDK board support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <errno.h>
+#include <fsl_esdhc.h>
+#include <fuse.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define EEPROM_I2C_ADDRESS	0x50
+
+#define PC			MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+		 .gp = IMX_GPIO_NR(3, 28)
+	 }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		 .gp = IMX_GPIO_NR(4, 13)
+	 }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+		 .gp = IMX_GPIO_NR(1, 6)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+		 .gp = IMX_GPIO_NR(3, 28)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		 .gp = IMX_GPIO_NR(4, 13)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+		 .gp = IMX_GPIO_NR(1, 6)
+	 }
+};
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static void eth_phy_reset(void)
+{
+	/* Reset PHY */
+	gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(5, 0), 1);
+
+	/* Enable VIO */
+	gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
+
+	/*
+	 * KSZ9021 PHY needs at least 10 mSec after PHY reset
+	 * is released to stabilize
+	 */
+	mdelay(10);
+}
+
+static int setup_fec_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set gpr1[21] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+
+	setup_fec_clock();
+
+	eth_phy_reset();
+
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return -EINVAL;
+
+	/* Scan PHY 0 */
+	phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("Ethernet PHY not found!\n");
+		return -EINVAL;
+	}
+
+	return fec_probe(bis, -1, base, bus, phydev);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 16)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 8)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{ USDHC2_BASE_ADDR },
+	{ USDHC3_BASE_ADDR },
+	{ USDHC4_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		return gpio_get_value(USDHC2_CD_GPIO);
+	case USDHC3_BASE_ADDR:
+		return !gpio_get_value(USDHC3_CD_GPIO);
+	case USDHC4_BASE_ADDR:
+		return 1; /* eMMC/uSDHC4 is always present */
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SD interface
+	 * mmc1                    micro SD
+	 * mmc2                    eMMC
+	 */
+	gpio_direction_input(USDHC2_CD_GPIO);
+	gpio_direction_input(USDHC3_CD_GPIO);
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * Set daisy chain for otg_pin_id on MX6Q.
+	 * For MX6DL, this bit is reserved.
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_HOST;
+}
+
+/* Use only Port 1 == DHCOM USB Host 1 */
+int board_ehci_hcd_init(int port)
+{
+	if (port == 1)
+		return 0;
+	else
+		return -ENODEV;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+static int setup_dhcom_mac_from_fuse(void)
+{
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		return 0;
+
+	imx_get_mac_from_fuse(0, enetaddr);
+
+	if (is_valid_ethaddr(enetaddr)) {
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+		return 0;
+	}
+
+	ret = i2c_set_bus_num(2);
+	if (ret) {
+		printf("Error switching I2C bus!\n");
+		return ret;
+	}
+
+	ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
+	if (ret) {
+		printf("Error reading configuration EEPROM!\n");
+		return ret;
+	}
+
+	if (is_valid_ethaddr(enetaddr))
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return IMX_GPIO_NR(2, 30);
+	else
+		return -1;
+}
+#endif
+
+int board_init(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Enable eim_slow clocks */
+	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+#ifdef CONFIG_SYS_I2C_MXC
+	if (is_mx6dq()) {
+		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
+	} else {
+		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
+	}
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_dhcom_mac_from_fuse();
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+#define HW_CODE_BIT_0	IMX_GPIO_NR(2, 19)
+#define HW_CODE_BIT_1	IMX_GPIO_NR(6, 6)
+#define HW_CODE_BIT_2	IMX_GPIO_NR(2, 16)
+
+static int board_get_hwcode(void)
+{
+	int hw_code;
+
+	gpio_direction_input(HW_CODE_BIT_0);
+	gpio_direction_input(HW_CODE_BIT_1);
+	gpio_direction_input(HW_CODE_BIT_2);
+
+	/* HW 100 + HW 200 = 00b; HW 300 = 01b */
+	hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
+		   (gpio_get_value(HW_CODE_BIT_1) << 1) |
+		    gpio_get_value(HW_CODE_BIT_0)) + 2;
+
+	return hw_code;
+}
+
+int board_late_init(void)
+{
+	u32 hw_code;
+	char buf[16];
+
+	hw_code = board_get_hwcode();
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6DL:
+		snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6D:
+		snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6Q:
+		snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
+		break;
+	default:
+		snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
+		break;
+	}
+
+	env_set("dhcom", buf);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DHCOM i.MX6\n");
+	return 0;
+}

board/dhelectronics/dh_imx6/dh_imx6_spl.c

@@ -0,0 +1,399 @@
+/*
+ * DHCOM DH-iMX6 PDK SPL support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fuse.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+
+#define ENET_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define SPI_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL							\
+	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |	\
+	 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
+	.p0_mpwldectrl0	= 0x001F001F,
+	.p0_mpwldectrl1	= 0x001F001F,
+	.p1_mpwldectrl0	= 0x00440044,
+	.p1_mpwldectrl1	= 0x00440044,
+	.p0_mpdgctrl0	= 0x434B0350,
+	.p0_mpdgctrl1	= 0x034C0359,
+	.p1_mpdgctrl0	= 0x434B0350,
+	.p1_mpdgctrl1	= 0x03650348,
+	.p0_mprddlctl	= 0x4436383B,
+	.p1_mprddlctl	= 0x39393341,
+	.p0_mpwrdlctl	= 0x35373933,
+	.p1_mpwrdlctl	= 0x48254A36,
+};
+
+static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 64,
+	.banks		= 8,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize		= 2,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,	/* 32Gb per CS */
+	.ncs		= 1,	/* single chip select */
+	.cs1_mirror	= 0,
+	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat		= 1,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* Board ID */
+static iomux_v3_cfg_t const hwcode_pads[] = {
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_boardid(void)
+{
+	/* HW code pins: Setup alternate function and configure pads */
+	SETUP_IOMUX_PADS(hwcode_pads);
+}
+
+/* GPIO */
+static iomux_v3_cfg_t const gpio_pads[] = {
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_gpio(void)
+{
+	SETUP_IOMUX_PADS(gpio_pads);
+}
+
+/* Ethernet */
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	/* SMSC PHY Reset */
+	IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_VIO_GPIO */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_Interrupt - (not used) */
+	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+}
+
+/* SD interface */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* onboard microSD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* eMMC */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/* SD */
+static void setup_iomux_sd(void)
+{
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+/* SPI */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS0 */
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+static void setup_iomux_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return IMX_GPIO_NR(2, 30);
+	else
+		return -1;
+}
+
+/* UART */
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+/* USB */
+static iomux_v3_cfg_t const usb_pads[] = {
+	IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_usb(void)
+{
+	SETUP_IOMUX_PADS(usb_pads);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	setup_iomux_boardid();
+	setup_iomux_gpio();
+	setup_iomux_enet();
+	setup_iomux_sd();
+	setup_iomux_spi();
+	setup_iomux_uart();
+	setup_iomux_usb();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Start the DDR DRAM */
+	if (is_mx6dq())
+		mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
+				 &dhcom6dq_grp_ioregs);
+	else
+		mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
+				  &dhcom6sdl_grp_ioregs);
+	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&dhcom_ddr_info);
+	mmdc_do_dqs_calibration(&dhcom_ddr_info);
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}

board/el/el6x/el6x.c

@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include <asm/arch/mx6-ddr.h>

board/embest/mx6boards/mx6boards.c

@@ -26,6 +26,7 @@
 #include <asm/mach-imx/spi.h>
 #include <asm/mach-imx/video.h>
 #include <i2c.h>
+#include <input.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>

board/engicam/icorem6_rqs/icorem6_rqs.c

@@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_ENV_IS_IN_MMC
 int board_mmc_get_env_dev(int devno)
 {
-	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
-	return (devno == 3) ? 1 : 0;
+	return devno;
 }
 #endif
 

board/freescale/mx51evk/mx51evk.c

@@ -15,6 +15,7 @@
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/mx5_video.h>
 #include <i2c.h>
+#include <input.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <power/pmic.h>

board/freescale/mx53loco/mx53loco.c

@@ -17,6 +17,7 @@
 #include <asm/mach-imx/mx5_video.h>
 #include <netdev.h>
 #include <i2c.h>
+#include <input.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/gpio.h>

board/freescale/mx6sabreauto/mx6sabreauto.c

@@ -24,6 +24,7 @@
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/mach-imx/video.h>
 #include <asm/arch/crm_regs.h>

board/freescale/mx6sabresd/mx6sabresd.c

@@ -10,6 +10,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
+#include <asm/mach-imx/spi.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
@@ -25,10 +26,12 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 #include <usb.h>
+#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -620,9 +623,6 @@ int board_ehci_power(int port, int on)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
 
 	return 0;
 }
@@ -639,6 +639,9 @@ int board_init(void)
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif

board/ge/bx50v3/bx50v3.c

@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
+#include <input.h>
 #include <pwm.h>
 #include <stdlib.h>
 #include "vpd_reader.h"

board/logicpd/imx6/imx6logic.c

@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <input.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/io.h>

board/solidrun/mx6cuboxi/mx6cuboxi.c

@@ -308,13 +308,8 @@ int board_ehci_hcd_init(int port)
 
 int board_early_init_f(void)
 {
-	int ret = 0;
 	setup_iomux_uart();
 
-#ifdef CONFIG_VIDEO_IPUV3
-	ret = setup_display();
-#endif
-
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
@@ -322,15 +317,21 @@ int board_early_init_f(void)
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
-	return ret;
+	return 0;
 }
 
 int board_init(void)
 {
+	int ret = 0;
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	return 0;
+#ifdef CONFIG_VIDEO_IPUV3
+	ret = setup_display();
+#endif
+
+	return ret;
 }
 
 static bool is_hummingboard(void)

board/technologic/ts4800/ts4800.c

@@ -18,6 +18,7 @@
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/mx5_video.h>
 #include <mmc.h>
+#include <input.h>
 #include <fsl_esdhc.h>
 #include <mc13892.h>
 

board/toradex/apalis_imx6/apalis_imx6.c

@@ -30,6 +30,7 @@
 #include <dm/platdata.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
+#include <input.h>
 #include <imx_thermal.h>
 #include <linux/errno.h>
 #include <malloc.h>
@@ -756,10 +757,6 @@ int board_early_init_f(void)
 #else
 	setup_iomux_dce_uart();
 #endif
-
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
 	return 0;
 }
 
@@ -781,6 +778,10 @@ int board_init(void)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 	(void) pmic_init();
 #endif

board/toradex/colibri_imx6/colibri_imx6.c

@@ -29,6 +29,7 @@
 #include <dm/platdata.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
+#include <input.h>
 #include <imx_thermal.h>
 #include <linux/errno.h>
 #include <malloc.h>
@@ -630,9 +631,6 @@ int board_early_init_f(void)
 					 ARRAY_SIZE(pwr_intb_pads));
 	setup_iomux_uart();
 
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
 	return 0;
 }
 
@@ -653,6 +651,10 @@ int board_init(void)
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
 
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+
 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 	(void) pmic_init();
 #endif

board/wandboard/wandboard.c

@@ -30,6 +30,8 @@
 #include <phy.h>
 #include <input.h>
 #include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,8 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)
 #define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)
 #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
+#define ETH_PHY_AR8035_POWER	IMX_GPIO_NR(7, 13)
 #define REV_DETECTION		IMX_GPIO_NR(2, 28)
 
+static bool with_pmic;
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -107,6 +112,11 @@ static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
+static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
+	/* AR8035 POWER */
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const rev_detection_pad[] = {
 	IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
@@ -120,6 +130,14 @@ static void setup_iomux_enet(void)
 {
 	SETUP_IOMUX_PADS(enet_pads);
 
+	if (with_pmic) {
+		SETUP_IOMUX_PADS(enet_ar8035_power_pads);
+		/* enable AR8035 POWER */
+		gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
+	}
+	/* wait until 3.3V of PHY and clock become stable */
+	mdelay(10);
+
 	/* Reset AR8031 PHY */
 	gpio_direction_output(ETH_PHY_RESET, 0);
 	mdelay(10);
@@ -192,6 +210,7 @@ int board_mmc_init(bd_t *bis)
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
+	int mask;
 
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
@@ -199,7 +218,12 @@ static int ar8031_phy_fixup(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
+	if (with_pmic)
+		mask = 0xffe7;	/* AR8035 */
+	else
+		mask = 0xffe3;	/* AR8031 */
+
+	val &= mask;
 	val |= 0x18;
 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 
@@ -257,6 +281,40 @@ struct i2c_pads_info mx6dl_i2c2_pad_info = {
 	}
 };
 
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(1, 5)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(7, 11)
+	}
+};
+
 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
@@ -376,9 +434,6 @@ int board_eth_init(bd_t *bis)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
-#endif
 #ifdef CONFIG_SATA
 	/* Only mx6q wandboard has SATA */
 	if (is_cpu_type(MXC_CPU_MX6Q))
@@ -388,6 +443,31 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#define PMIC_I2C_BUS		2
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	u32 reg;
+
+	/* configure PFUZE100 PMIC */
+	power_pfuze100_init(PMIC_I2C_BUS);
+	p = pmic_get("PFUZE100");
+	if (p && !pmic_probe(p)) {
+		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+		printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+		with_pmic = true;
+
+		/* Set VGEN2 to 1.5V and enable */
+		pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
+		reg &= ~(LDO_VOL_MASK);
+		reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+		pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
+	}
+
+	return 0;
+}
+
 /*
  * Do not overwrite the console
  * Use always serial for U-Boot console
@@ -417,6 +497,14 @@ static bool is_revc1(void)
 		return false;
 }
 
+static bool is_revd1(void)
+{
+	if (with_pmic)
+		return true;
+	else
+		return false;
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
@@ -429,7 +517,9 @@ int board_late_init(void)
 	else
 		env_set("board_rev", "MX6DL");
 
-	if (is_revc1())
+	if (is_revd1())
+		env_set("board_name", "D1");
+	else if (is_revc1())
 		env_set("board_name", "C1");
 	else
 		env_set("board_name", "B1");
@@ -444,10 +534,15 @@ int board_init(void)
 
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-	if (is_mx6dq())
+	if (is_mx6dq()) {
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
-	else
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+	} else {
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+	}
+
+	setup_display();
 #endif
 
 	return 0;
@@ -455,7 +550,9 @@ int board_init(void)
 
 int checkboard(void)
 {
-	if (is_revc1())
+	if (is_revd1())
+		puts("Board: Wandboard rev D1\n");
+	else if (is_revc1())
 		puts("Board: Wandboard rev C1\n");
 	else
 		puts("Board: Wandboard rev B1\n");

configs/cl-som-imx7_defconfig

@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_CL_SOM_IMX7=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="CL-SOM-iMX7 # "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_OF_LIBFDT=y

configs/dh_imx6_defconfig

@@ -0,0 +1,51 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y

configs/imx6qdl_icore_mmc_defconfig

@@ -36,7 +36,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
 CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_BLK is not set
 CONFIG_SYS_I2C_MXC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y

configs/imx6qdl_icore_rqs_defconfig

@@ -33,7 +33,6 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
 CONFIG_ENV_IS_IN_MMC=y
-# CONFIG_BLK is not set
 CONFIG_SYS_I2C_MXC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y

configs/mx25pdk_defconfig

@@ -14,7 +14,8 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FS_FAT=y
 CONFIG_OF_LIBFDT=y

configs/mx53loco_defconfig

@@ -8,7 +8,6 @@ CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MMC=y

configs/mx6slevk_defconfig

@@ -12,6 +12,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set

configs/mx6slevk_spl_defconfig

@@ -20,6 +20,7 @@ CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y

configs/mx7ulp_evk_defconfig

@@ -4,6 +4,7 @@ CONFIG_TARGET_MX7ULP_EVK=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y

configs/wandboard_defconfig

@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
 CONFIG_SPL_EXT_SUPPORT=y

doc/README.imx6

@@ -110,34 +110,8 @@ issue the command:
 
 	sudo ../imx_usb_loader/imx_usb -v u-boot.imx
 
-Getting U-Boot when SPL support is active, it requires
-two downloads. imx_usb_loader downloads the SPL into
-OCRAM and starts it. SPL will check for a valid u-boot.img, and
-because it is not found, it will wait for it using the y-modem
-protocol via the console.
-
-A first install is then possible by combining imx_usb_loader with
-another tool such as kermit.
-
-sudo ../imx_usb_loader/imx_usb -v SPL
-kermit kermit_uboot
-
-and kermit_uboot contains something like this (set line should be adjusted):
-
-set line /dev/ttyUSB1
-set speed 115200
-SET CARRIER-WATCH OFF
-set flow-control none
-set handshake none
-set prefixing all
-set file type bin
-set protocol ymodem
-send u-boot.img
-c
-
-The last "c" command tells kermit (from ckermit package in most distros)
-to switch from command line mode to communication mode, and when the
-script is finished, the U-Boot prompt is shown in the same shell.
+In order to load SPL and u-boot.img via imx_usb_loader tool,
+please refer to doc/README.sdp.
 
 3. Using Secure Boot on i.MX6 machines with SPL support
 -------------------------------------------------------
@@ -186,4 +160,4 @@ cat SPL csf-SPL.bin > SPL-signed
 cat u-boot-ivt.img csf-u-boot.bin > u-boot-signed.img
 
 These two signed binaries can be used on an i.MX6 in closed
-configuration when the according SRK Table Hash has been flashed.
+configuration when the according SRK Table Hash has been flashed.

doc/README.sdp

@@ -14,7 +14,7 @@ SoC's recovery mechanism is using.
 The SDP protocol over USB is a USB HID class protocol. USB HID class
 protocols allow to access a USB device without OS specific drivers. The
 U-Boot implementation has primarly been tested using the open source
-imx_loader utility (https://github.com/toradex/imx_loader).
+imx_loader utility (https://github.com/boundarydevices/imx_usb_loader).
 
 The host side utilities are typically capable to interpret the i.MX
 specific image header (see doc/README.imximage). There are extensions

drivers/pci/pcie_imx.c

@@ -431,7 +431,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 /*
  * Initial bus setup
  */
-static int imx6_pcie_assert_core_reset(void)
+static int imx6_pcie_assert_core_reset(bool prepare_for_boot)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
@@ -459,7 +459,7 @@ static int imx6_pcie_assert_core_reset(void)
 	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
 	 * indication that the bootloader activated the link.
 	 */
-	if (is_mx6dq()) {
+	if (is_mx6dq() && prepare_for_boot) {
 		u32 val, gpr1, gpr12;
 
 		gpr1 = readl(&iomuxc_regs->gpr[1]);
@@ -605,7 +605,7 @@ static int imx_pcie_link_up(void)
 	uint32_t tmp;
 	int count = 0;
 
-	imx6_pcie_assert_core_reset();
+	imx6_pcie_assert_core_reset(false);
 	imx6_pcie_init_phy();
 	imx6_pcie_deassert_core_reset();
 
@@ -687,7 +687,7 @@ void imx_pcie_init(void)
 
 void imx_pcie_remove(void)
 {
-	imx6_pcie_assert_core_reset();
+	imx6_pcie_assert_core_reset(true);
 }
 
 /* Probe function. */

include/configs/apalis_imx6.h

@@ -23,7 +23,6 @@
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
-#define CONFIG_SPL_PAD_TO		0x11000 /* 4k IVT/DCD, 64k SPL */
 #endif
 
 #define CONFIG_CMDLINE_TAG

include/configs/cl-som-imx7.h

@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) 2015 CompuLab, Ltd.
+ *
+ * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CL_SOM_IMX7_CONFIG_H
+#define __CL_SOM_IMX7_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_DBG_MONITOR
+
+#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Uncomment to enable secure boot support */
+/* #define CONFIG_SECURE_BOOT */
+#define CONFIG_CSF_SIZE			0x4000
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2		/* Enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define SYS_I2C_BUS_SOM			0
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	SYS_I2C_BUS_SOM
+
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
+
+#undef CONFIG_SYS_AUTOLOAD
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_BOOTDELAY
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=off\0" \
+	"script=boot.scr\0" \
+	"loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \
+	"loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \
+	"loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \
+	"bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \
+	"storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \
+	"kernel=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=imx7d-sbc-imx7.dtb\0" \
+	"fdtaddr=0x83000000\0" \
+	"mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
+	"usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
+	"doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \
+	"mmcbootscript=" \
+		"if run mmc_config; then " \
+			"setenv storagetype mmc;" \
+			"setenv storagedev ${mmcdev}:${mmcpart};" \
+			"if run loadscript; then " \
+				"run bootscript; " \
+			"fi; " \
+		"fi;\0" \
+	"mmcboot=" \
+		"if run mmc_config; then " \
+			"setenv storagetype mmc;" \
+			"setenv storagedev ${mmcdev}:${mmcpart};" \
+			"if run loadkernel; then " \
+				"if run loadfdt; then " \
+					"run storagebootcmd;" \
+				"fi; " \
+			"fi; " \
+		"fi;\0" \
+	"sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \
+		"run mmcbootscript\0" \
+	"usbbootscript=setenv usbdev ${usbdev_def}; " \
+		"setenv storagetype usb;" \
+		"setenv storagedev ${usbdev}:${usbpart};" \
+		"if run loadscript; then " \
+			"run bootscript; " \
+		"fi; " \
+	"sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \
+	"emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
+	"emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"echo SD boot attempt ...; run sdbootscript; run sdboot; " \
+	"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
+	"echo USB boot attempt ...; run usbbootscript; "
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPI Flash support */
+#define CONFIG_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+
+/* MMC Config*/
+#define CONFIG_FSL_USDHC
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC1_BASE_ADDR
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2" /* USDHC1 */
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#endif
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* Uncomment to enable iMX thermal driver support */
+/*#define CONFIG_IMX_THERMAL*/
+
+/* SPL */
+#include "imx7_spl.h"
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_H */

include/configs/colibri_imx6.h

@@ -21,7 +21,6 @@
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
-#define CONFIG_SPL_PAD_TO		0x11000 /* 4k IVT/DCD, 64k SPL */
 #endif
 
 #define CONFIG_CMDLINE_TAG

include/configs/dh_imx6.h

@@ -0,0 +1,191 @@
+/*
+ * DHCOM DH-iMX6 PDK board configuration
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DH_IMX6_CONFIG_H
+#define __DH_IMX6_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/*
+ * SPI NOR layout:
+ * 0x00_0000-0x00_ffff ... U-Boot SPL
+ * 0x01_0000-0x0f_ffff ... U-Boot
+ * 0x10_0000-0x10_ffff ... U-Boot env #1
+ * 0x11_0000-0x11_ffff ... U-Boot env #2
+ * 0x12_0000-0x1f_ffff ... UNUSED
+ */
+
+/* SPL */
+#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x11400
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.imx"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SUPPORT_RAW_INITRD	/* bootz raw initrd support */
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_BZIP2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
+
+/* Bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* FEC ethernet */
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_ARP_TIMEOUT		200UL
+
+/* Fuses */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* SPI Flash Configs */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2 /* Enabled USB controller number */
+#endif
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS	60000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"console=ttymxc0,115200\0"	\
+	"fdt_addr=0x18000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"ramdisk_addr_r=0x18000000\0"	\
+	"scriptaddr=0x14000000\0"	\
+	"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 1) \
+	func(SATA, sata, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#endif	/* __DH_IMX6_CONFIG_H */

include/configs/imx7_spl.h

@@ -0,0 +1,61 @@
+/*
+ * SPL definitions for the i.MX7 SPL
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX7_SPL_CONFIG_H
+#define __IMX7_SPL_CONFIG_H
+
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_FRAMEWORK
+
+/*
+ * see figure 6-22 in i.MX 7Dual/Solo Reference manuals:
+ *  - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to
+ *    0x00946C00.
+ *  - Set the stack at the end of the free area section, at 0x00946BB8.
+ *  - The BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
+ *    64KB is more then enough for the SPL.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x00911000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_STACK		0x00946BB8
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x11000
+
+/* MMC support */
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_MONITOR_LEN			409600	/* 400 KB */
+#endif
+
+/* Define the payload for FAT/EXT support */
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+# ifdef CONFIG_OF_CONTROL
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot-dtb.img"
+# else
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# endif
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR      0x88200000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x100000		/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x88300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000		/* 1 MB */
+#define CONFIG_SYS_TEXT_BASE           0x87800000
+
+#endif /* CONFIG_SPL */
+
+#endif /* __IMX7_SPL_CONFIG_H */

include/configs/mx25pdk.h

@@ -58,8 +58,6 @@
 #define CONFIG_ENV_SIZE        (8 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV		0
 
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
 /* U-Boot general configuration */
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
@@ -70,6 +68,9 @@
 
 /* U-Boot commands */
 
+/* Filesystem support */
+#define CONFIG_FS_EXT4
+
 /* Ethernet */
 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_MXC_PHYADDR		0x1f
@@ -138,11 +139,11 @@
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
-		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \

include/configs/mx6slevk.h

@@ -53,9 +53,9 @@
 	"ip_dyn=yes\0" \
 	"mmcdev=1\0" \
 	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"finduuid=part uuid mmc 1:2 uuid\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=${mmcroot}\0" \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
@@ -63,6 +63,7 @@
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \

include/configs/mx7ulp_evk.h

@@ -89,7 +89,6 @@
 #define PHYS_SDRAM_SIZE			SZ_1G
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
-#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_LOADADDR             0x60800000
 

include/configs/topic_miami.h

@@ -134,7 +134,6 @@
 #undef CONFIG_DISPLAY_BOARDINFO
 
 /* Further tweaks to reduce image size */
-#undef CONFIG_CMD_BOOTZ
 #undef CONFIG_CMD_NET
 
 #endif /* __CONFIG_TOPIC_MIAMI_H */

include/configs/wandboard.h

@@ -13,6 +13,7 @@
 #include "mx6_common.h"
 
 #include "imx6_spl.h"
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_WANDBOARD_IMX6
 
@@ -44,6 +45,12 @@
 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
 /* MMC Configuration */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
@@ -102,6 +109,10 @@
 			"fi; "	\
 		"fi\0" \
 	"findfdt="\
+		"if test $board_name = D1 && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
+		"if test $board_name = D1 && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \
 		"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
 			"setenv fdtfile imx6q-wandboard.dtb; fi; " \
 		"if test $board_name = C1 && test $board_rev = MX6DL ; then " \

include/configs/xpress.h

@@ -18,7 +18,7 @@
 #define CONFIG_SYS_MALLOC_LEN		(16 << 20)
 
 #define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_MXC_UART_BASE		MX6UL_UART7_BASE_ADDR
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
@@ -87,7 +87,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"console=ttymxc0\0" \
+	"console=ttymxc6\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=undefined\0" \

include/usb/ehci-ci.h

@@ -280,6 +280,7 @@ struct usb_ehci {
 int usb_phy_mode(int port);
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
+int board_ehci_power(int port, int on);
 int board_usb_phy_mode(int port);
 
 #endif /* _EHCI_CI_H */