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@@ -81,13 +81,23 @@
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#define CEVA_TRANS_CFG 0x08000029
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#define CEVA_AXICC_CFG 0x3fffffff
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+/* for ls1021a */
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+#define LS1021_AHCI_VEND_AXICC 0xC0
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+#define LS1021_CEVA_PHY2_CFG 0x28183414
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+#define LS1021_CEVA_PHY3_CFG 0x0e080e06
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+#define LS1021_CEVA_PHY4_CFG 0x064a080b
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+#define LS1021_CEVA_PHY5_CFG 0x2aa86470
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+
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/* ecc addr-val pair */
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#define ECC_DIS_ADDR_CH2 0x80000000
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-#define ECC_DIS_VAL_CH2 0x20140520
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+#define ECC_DIS_VAL_CH2 0x20140520
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+#define SATA_ECC_REG_ADDR 0x20220520
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+#define SATA_ECC_DISABLE 0x00020000
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enum ceva_soc {
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CEVA_1V84,
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CEVA_LS1012A,
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+ CEVA_LS1021A,
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CEVA_LS1043A,
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};
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@@ -114,6 +124,18 @@ static int ceva_init_sata(struct ceva_sata_priv *priv)
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writel(tmp, base + AHCI_VEND_PTC);
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break;
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+ case CEVA_LS1021A:
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+ writel(SATA_ECC_DISABLE, SATA_ECC_REG_ADDR);
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+ writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
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+ writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
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+ writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
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+ writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
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+ writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
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+ writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
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+ if (priv->flag & FLAG_COHERENT)
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+ writel(CEVA_AXICC_CFG, base + LS1021_AHCI_VEND_AXICC);
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+ break;
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+
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case CEVA_LS1012A:
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case CEVA_LS1043A:
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writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2);
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@@ -146,6 +168,7 @@ static int sata_ceva_probe(struct udevice *dev)
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static const struct udevice_id sata_ceva_ids[] = {
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{ .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
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{ .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
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+ { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
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{ .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
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{ }
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};
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