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@@ -445,9 +445,6 @@ static unsigned char spd_read(uchar chip, uint addr)
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phys_size_t initdram(int board_type)
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{
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unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
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- unsigned char spd0[MAX_SPD_BYTES];
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- unsigned char spd1[MAX_SPD_BYTES];
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- unsigned char *dimm_spd[MAXDIMMS];
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unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
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unsigned long num_dimm_banks; /* on board dimm banks */
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unsigned long val;
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@@ -457,12 +454,6 @@ phys_size_t initdram(int board_type)
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num_dimm_banks = sizeof(iic0_dimm_addr);
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- /*------------------------------------------------------------------
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- * Set up an array of SPD matrixes.
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- *-----------------------------------------------------------------*/
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- dimm_spd[0] = spd0;
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- dimm_spd[1] = spd1;
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-
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/*------------------------------------------------------------------
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* Reset the DDR-SDRAM controller.
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*-----------------------------------------------------------------*/
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@@ -1000,7 +991,6 @@ static void program_copt1(unsigned long *dimm_populated,
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unsigned long attribute = 0;
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unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
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unsigned long bankcount;
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- unsigned long ddrtype;
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unsigned long val;
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#ifdef CONFIG_DDR_ECC
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@@ -1045,8 +1035,6 @@ static void program_copt1(unsigned long *dimm_populated,
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else /* bank count = 8 */
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mcopt1 |= SDRAM_MCOPT1_8_BANKS;
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- /* test DDR type */
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- ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
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/* test for buffered/unbuffered, registered, differential clocks */
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registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
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attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
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@@ -1500,7 +1488,6 @@ static void program_mode(unsigned long *dimm_populated,
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else
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sdram_ddr1 = FALSE;
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- /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
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cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
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debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
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@@ -2490,12 +2477,6 @@ static void DQS_calibration_process(void)
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unsigned long val;
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long rffd_average;
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long max_start;
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- long min_end;
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- unsigned long begin_rqfd[MAXRANKS];
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- unsigned long begin_rffd[MAXRANKS];
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- unsigned long end_rqfd[MAXRANKS];
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- unsigned long end_rffd[MAXRANKS];
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- char window_found;
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unsigned long dlycal;
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unsigned long dly_val;
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unsigned long max_pass_length;
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@@ -2506,6 +2487,7 @@ static void DQS_calibration_process(void)
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unsigned char fail_found;
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unsigned char pass_found;
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#if !defined(CONFIG_DDR_RQDC_FIXED)
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+ int window_found;
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u32 rqdc_reg;
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u32 rqfd;
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u32 rqfd_start;
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@@ -2559,16 +2541,6 @@ calibration_loop:
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#endif /* CONFIG_DDR_RQDC_FIXED */
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max_start = 0;
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- min_end = 0;
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- begin_rqfd[0] = 0;
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- begin_rffd[0] = 0;
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- begin_rqfd[1] = 0;
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- begin_rffd[1] = 0;
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- end_rqfd[0] = 0;
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- end_rffd[0] = 0;
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- end_rqfd[1] = 0;
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- end_rffd[1] = 0;
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- window_found = FALSE;
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max_pass_length = 0;
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max_start = 0;
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@@ -2576,7 +2548,6 @@ calibration_loop:
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current_pass_length = 0;
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current_fail_length = 0;
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current_start = 0;
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- window_found = FALSE;
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fail_found = FALSE;
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pass_found = FALSE;
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@@ -2621,7 +2592,6 @@ calibration_loop:
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if (fail_found == FALSE) {
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fail_found = TRUE;
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} else if (pass_found == TRUE) {
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- window_found = TRUE;
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break;
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}
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}
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