|
|
@@ -10,11 +10,11 @@
|
|
|
*/
|
|
|
|
|
|
#include <common.h>
|
|
|
+#include <dm.h>
|
|
|
#include <net.h>
|
|
|
#include <netdev.h>
|
|
|
#include <config.h>
|
|
|
-#include <fdtdec.h>
|
|
|
-#include <libfdt.h>
|
|
|
+#include <console.h>
|
|
|
#include <malloc.h>
|
|
|
#include <asm/io.h>
|
|
|
#include <phy.h>
|
|
|
@@ -25,6 +25,8 @@
|
|
|
#include <asm/arch/sys_proto.h>
|
|
|
#include <asm-generic/errno.h>
|
|
|
|
|
|
+DECLARE_GLOBAL_DATA_PTR;
|
|
|
+
|
|
|
#if !defined(CONFIG_PHYLIB)
|
|
|
# error XILINX_GEM_ETHERNET requires PHYLIB
|
|
|
#endif
|
|
|
@@ -167,14 +169,14 @@ struct zynq_gem_priv {
|
|
|
int phyaddr;
|
|
|
u32 emio;
|
|
|
int init;
|
|
|
+ struct zynq_gem_regs *iobase;
|
|
|
phy_interface_t interface;
|
|
|
struct phy_device *phydev;
|
|
|
struct mii_dev *bus;
|
|
|
};
|
|
|
|
|
|
-static inline int mdio_wait(struct eth_device *dev)
|
|
|
+static inline int mdio_wait(struct zynq_gem_regs *regs)
|
|
|
{
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
u32 timeout = 20000;
|
|
|
|
|
|
/* Wait till MDIO interface is ready to accept a new transaction. */
|
|
|
@@ -192,13 +194,13 @@ static inline int mdio_wait(struct eth_device *dev)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
|
|
|
- u32 op, u16 *data)
|
|
|
+static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
|
|
|
+ u32 op, u16 *data)
|
|
|
{
|
|
|
u32 mgtcr;
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
|
|
|
- if (mdio_wait(dev))
|
|
|
+ if (mdio_wait(regs))
|
|
|
return 1;
|
|
|
|
|
|
/* Construct mgtcr mask for the operation */
|
|
|
@@ -209,7 +211,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
|
|
|
/* Write mgtcr and wait for completion */
|
|
|
writel(mgtcr, ®s->phymntnc);
|
|
|
|
|
|
- if (mdio_wait(dev))
|
|
|
+ if (mdio_wait(regs))
|
|
|
return 1;
|
|
|
|
|
|
if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
|
|
|
@@ -218,12 +220,13 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
|
|
|
+static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
|
|
|
+ u32 regnum, u16 *val)
|
|
|
{
|
|
|
u32 ret;
|
|
|
|
|
|
- ret = phy_setup_op(dev, phy_addr, regnum,
|
|
|
- ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
|
|
|
+ ret = phy_setup_op(priv, phy_addr, regnum,
|
|
|
+ ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
|
|
|
|
|
|
if (!ret)
|
|
|
debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
|
|
|
@@ -232,29 +235,30 @@ static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
|
|
|
+static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
|
|
|
+ u32 regnum, u16 data)
|
|
|
{
|
|
|
debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
|
|
|
regnum, data);
|
|
|
|
|
|
- return phy_setup_op(dev, phy_addr, regnum,
|
|
|
- ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
|
|
|
+ return phy_setup_op(priv, phy_addr, regnum,
|
|
|
+ ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
|
|
|
}
|
|
|
|
|
|
-static void phy_detection(struct eth_device *dev)
|
|
|
+static int phy_detection(struct udevice *dev)
|
|
|
{
|
|
|
int i;
|
|
|
u16 phyreg;
|
|
|
struct zynq_gem_priv *priv = dev->priv;
|
|
|
|
|
|
if (priv->phyaddr != -1) {
|
|
|
- phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
|
|
|
+ phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
|
|
|
if ((phyreg != 0xFFFF) &&
|
|
|
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
|
|
|
/* Found a valid PHY address */
|
|
|
debug("Default phy address %d is valid\n",
|
|
|
priv->phyaddr);
|
|
|
- return;
|
|
|
+ return 0;
|
|
|
} else {
|
|
|
debug("PHY address is not setup correctly %d\n",
|
|
|
priv->phyaddr);
|
|
|
@@ -266,33 +270,36 @@ static void phy_detection(struct eth_device *dev)
|
|
|
if (priv->phyaddr == -1) {
|
|
|
/* detect the PHY address */
|
|
|
for (i = 31; i >= 0; i--) {
|
|
|
- phyread(dev, i, PHY_DETECT_REG, &phyreg);
|
|
|
+ phyread(priv, i, PHY_DETECT_REG, &phyreg);
|
|
|
if ((phyreg != 0xFFFF) &&
|
|
|
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
|
|
|
/* Found a valid PHY address */
|
|
|
priv->phyaddr = i;
|
|
|
debug("Found valid phy address, %d\n", i);
|
|
|
- return;
|
|
|
+ return 0;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
printf("PHY is not detected\n");
|
|
|
+ return -1;
|
|
|
}
|
|
|
|
|
|
-static int zynq_gem_setup_mac(struct eth_device *dev)
|
|
|
+static int zynq_gem_setup_mac(struct udevice *dev)
|
|
|
{
|
|
|
u32 i, macaddrlow, macaddrhigh;
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
+ struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
|
|
|
/* Set the MAC bits [31:0] in BOT */
|
|
|
- macaddrlow = dev->enetaddr[0];
|
|
|
- macaddrlow |= dev->enetaddr[1] << 8;
|
|
|
- macaddrlow |= dev->enetaddr[2] << 16;
|
|
|
- macaddrlow |= dev->enetaddr[3] << 24;
|
|
|
+ macaddrlow = pdata->enetaddr[0];
|
|
|
+ macaddrlow |= pdata->enetaddr[1] << 8;
|
|
|
+ macaddrlow |= pdata->enetaddr[2] << 16;
|
|
|
+ macaddrlow |= pdata->enetaddr[3] << 24;
|
|
|
|
|
|
/* Set MAC bits [47:32] in TOP */
|
|
|
- macaddrhigh = dev->enetaddr[4];
|
|
|
- macaddrhigh |= dev->enetaddr[5] << 8;
|
|
|
+ macaddrhigh = pdata->enetaddr[4];
|
|
|
+ macaddrhigh |= pdata->enetaddr[5] << 8;
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
writel(0, ®s->laddr[i][LADDR_LOW]);
|
|
|
@@ -307,15 +314,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
|
|
|
+static int zynq_phy_init(struct udevice *dev)
|
|
|
{
|
|
|
- u32 i;
|
|
|
- unsigned long clk_rate = 0;
|
|
|
- struct phy_device *phydev;
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
- struct zynq_gem_priv *priv = dev->priv;
|
|
|
- struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
|
|
|
- struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
|
|
|
+ int ret;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
const u32 supported = SUPPORTED_10baseT_Half |
|
|
|
SUPPORTED_10baseT_Full |
|
|
|
SUPPORTED_100baseT_Half |
|
|
|
@@ -323,6 +326,37 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
|
|
|
SUPPORTED_1000baseT_Half |
|
|
|
SUPPORTED_1000baseT_Full;
|
|
|
|
|
|
+ /* Enable only MDIO bus */
|
|
|
+ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
|
|
|
+
|
|
|
+ ret = phy_detection(dev);
|
|
|
+ if (ret) {
|
|
|
+ printf("GEM PHY init failed\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
|
|
|
+ priv->interface);
|
|
|
+ if (!priv->phydev)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ priv->phydev->supported = supported | ADVERTISED_Pause |
|
|
|
+ ADVERTISED_Asym_Pause;
|
|
|
+ priv->phydev->advertising = priv->phydev->supported;
|
|
|
+ phy_config(priv->phydev);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int zynq_gem_init(struct udevice *dev)
|
|
|
+{
|
|
|
+ u32 i;
|
|
|
+ unsigned long clk_rate = 0;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
+ struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
|
|
|
+ struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
|
|
|
+
|
|
|
if (!priv->init) {
|
|
|
/* Disable all interrupts */
|
|
|
writel(0xFFFFFFFF, ®s->idr);
|
|
|
@@ -384,25 +418,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
|
|
|
priv->init++;
|
|
|
}
|
|
|
|
|
|
- phy_detection(dev);
|
|
|
-
|
|
|
- /* interface - look at tsec */
|
|
|
- phydev = phy_connect(priv->bus, priv->phyaddr, dev,
|
|
|
- priv->interface);
|
|
|
-
|
|
|
- phydev->supported = supported | ADVERTISED_Pause |
|
|
|
- ADVERTISED_Asym_Pause;
|
|
|
- phydev->advertising = phydev->supported;
|
|
|
- priv->phydev = phydev;
|
|
|
- phy_config(phydev);
|
|
|
- phy_startup(phydev);
|
|
|
+ phy_startup(priv->phydev);
|
|
|
|
|
|
- if (!phydev->link) {
|
|
|
- printf("%s: No link.\n", phydev->dev->name);
|
|
|
+ if (!priv->phydev->link) {
|
|
|
+ printf("%s: No link.\n", priv->phydev->dev->name);
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
- switch (phydev->speed) {
|
|
|
+ switch (priv->phydev->speed) {
|
|
|
case SPEED_1000:
|
|
|
writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
|
|
|
®s->nwcfg);
|
|
|
@@ -420,7 +443,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
|
|
|
|
|
|
/* Change the rclk and clk only not using EMIO interface */
|
|
|
if (!priv->emio)
|
|
|
- zynq_slcr_gem_clk_setup(dev->iobase !=
|
|
|
+ zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
|
|
|
ZYNQ_GEM_BASEADDR0, clk_rate);
|
|
|
|
|
|
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
|
|
|
@@ -447,6 +470,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
|
|
|
if (get_timer(start) > timeout)
|
|
|
break;
|
|
|
|
|
|
+ if (ctrlc()) {
|
|
|
+ puts("Abort\n");
|
|
|
+ return -EINTR;
|
|
|
+ }
|
|
|
+
|
|
|
udelay(1);
|
|
|
}
|
|
|
|
|
|
@@ -456,11 +484,11 @@ static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
|
|
|
return -ETIMEDOUT;
|
|
|
}
|
|
|
|
|
|
-static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
|
|
|
+static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
|
|
|
{
|
|
|
u32 addr, size;
|
|
|
- struct zynq_gem_priv *priv = dev->priv;
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
struct emac_bd *current_bd = &priv->tx_bd[1];
|
|
|
|
|
|
/* Setup Tx BD */
|
|
|
@@ -501,10 +529,10 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
|
|
|
}
|
|
|
|
|
|
/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
|
|
|
-static int zynq_gem_recv(struct eth_device *dev)
|
|
|
+static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
|
{
|
|
|
int frame_len;
|
|
|
- struct zynq_gem_priv *priv = dev->priv;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
|
|
|
struct emac_bd *first_bd;
|
|
|
|
|
|
@@ -544,51 +572,41 @@ static int zynq_gem_recv(struct eth_device *dev)
|
|
|
return frame_len;
|
|
|
}
|
|
|
|
|
|
-static void zynq_gem_halt(struct eth_device *dev)
|
|
|
+static void zynq_gem_halt(struct udevice *dev)
|
|
|
{
|
|
|
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ struct zynq_gem_regs *regs = priv->iobase;
|
|
|
|
|
|
clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
|
|
|
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
|
|
|
}
|
|
|
|
|
|
-static int zynq_gem_miiphyread(const char *devname, uchar addr,
|
|
|
- uchar reg, ushort *val)
|
|
|
+static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
|
|
|
+ int devad, int reg)
|
|
|
{
|
|
|
- struct eth_device *dev = eth_get_dev();
|
|
|
+ struct zynq_gem_priv *priv = bus->priv;
|
|
|
int ret;
|
|
|
+ u16 val;
|
|
|
|
|
|
- ret = phyread(dev, addr, reg, val);
|
|
|
- debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
|
|
|
- return ret;
|
|
|
+ ret = phyread(priv, addr, reg, &val);
|
|
|
+ debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
|
|
|
+ return val;
|
|
|
}
|
|
|
|
|
|
-static int zynq_gem_miiphy_write(const char *devname, uchar addr,
|
|
|
- uchar reg, ushort val)
|
|
|
+static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
|
|
+ int reg, u16 value)
|
|
|
{
|
|
|
- struct eth_device *dev = eth_get_dev();
|
|
|
+ struct zynq_gem_priv *priv = bus->priv;
|
|
|
|
|
|
- debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
|
|
|
- return phywrite(dev, addr, reg, val);
|
|
|
+ debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
|
|
|
+ return phywrite(priv, addr, reg, value);
|
|
|
}
|
|
|
|
|
|
-int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
|
|
|
- int phy_addr, u32 emio)
|
|
|
+static int zynq_gem_probe(struct udevice *dev)
|
|
|
{
|
|
|
- struct eth_device *dev;
|
|
|
- struct zynq_gem_priv *priv;
|
|
|
void *bd_space;
|
|
|
-
|
|
|
- dev = calloc(1, sizeof(*dev));
|
|
|
- if (dev == NULL)
|
|
|
- return -1;
|
|
|
-
|
|
|
- dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
|
|
|
- if (dev->priv == NULL) {
|
|
|
- free(dev);
|
|
|
- return -1;
|
|
|
- }
|
|
|
- priv = dev->priv;
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
+ int ret;
|
|
|
|
|
|
/* Align rxbuffers to ARCH_DMA_MINALIGN */
|
|
|
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
|
|
|
@@ -603,69 +621,87 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
|
|
|
priv->tx_bd = (struct emac_bd *)bd_space;
|
|
|
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
|
|
|
|
|
|
- priv->phyaddr = phy_addr;
|
|
|
- priv->emio = emio;
|
|
|
-
|
|
|
-#ifndef CONFIG_ZYNQ_GEM_INTERFACE
|
|
|
- priv->interface = PHY_INTERFACE_MODE_MII;
|
|
|
-#else
|
|
|
- priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
|
|
|
-#endif
|
|
|
+ priv->bus = mdio_alloc();
|
|
|
+ priv->bus->read = zynq_gem_miiphy_read;
|
|
|
+ priv->bus->write = zynq_gem_miiphy_write;
|
|
|
+ priv->bus->priv = priv;
|
|
|
+ strcpy(priv->bus->name, "gem");
|
|
|
|
|
|
- sprintf(dev->name, "Gem.%lx", base_addr);
|
|
|
+ ret = mdio_register(priv->bus);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
|
|
|
- dev->iobase = base_addr;
|
|
|
+ zynq_phy_init(dev);
|
|
|
|
|
|
- dev->init = zynq_gem_init;
|
|
|
- dev->halt = zynq_gem_halt;
|
|
|
- dev->send = zynq_gem_send;
|
|
|
- dev->recv = zynq_gem_recv;
|
|
|
- dev->write_hwaddr = zynq_gem_setup_mac;
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- eth_register(dev);
|
|
|
+static int zynq_gem_remove(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
- miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
|
|
|
- priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
+ free(priv->phydev);
|
|
|
+ mdio_unregister(priv->bus);
|
|
|
+ mdio_free(priv->bus);
|
|
|
|
|
|
- return 1;
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-#if CONFIG_IS_ENABLED(OF_CONTROL)
|
|
|
-int zynq_gem_of_init(const void *blob)
|
|
|
+static const struct eth_ops zynq_gem_ops = {
|
|
|
+ .start = zynq_gem_init,
|
|
|
+ .send = zynq_gem_send,
|
|
|
+ .recv = zynq_gem_recv,
|
|
|
+ .stop = zynq_gem_halt,
|
|
|
+ .write_hwaddr = zynq_gem_setup_mac,
|
|
|
+};
|
|
|
+
|
|
|
+static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
|
|
|
{
|
|
|
+ struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
+ struct zynq_gem_priv *priv = dev_get_priv(dev);
|
|
|
int offset = 0;
|
|
|
- u32 ret = 0;
|
|
|
- u32 reg, phy_reg;
|
|
|
-
|
|
|
- debug("ZYNQ GEM: Initialization\n");
|
|
|
-
|
|
|
- do {
|
|
|
- offset = fdt_node_offset_by_compatible(blob, offset,
|
|
|
- "xlnx,ps7-ethernet-1.00.a");
|
|
|
- if (offset != -1) {
|
|
|
- reg = fdtdec_get_addr(blob, offset, "reg");
|
|
|
- if (reg != FDT_ADDR_T_NONE) {
|
|
|
- offset = fdtdec_lookup_phandle(blob, offset,
|
|
|
- "phy-handle");
|
|
|
- if (offset != -1)
|
|
|
- phy_reg = fdtdec_get_addr(blob, offset,
|
|
|
- "reg");
|
|
|
- else
|
|
|
- phy_reg = 0;
|
|
|
-
|
|
|
- debug("ZYNQ GEM: addr %x, phyaddr %x\n",
|
|
|
- reg, phy_reg);
|
|
|
-
|
|
|
- ret |= zynq_gem_initialize(NULL, reg,
|
|
|
- phy_reg, 0);
|
|
|
-
|
|
|
- } else {
|
|
|
- debug("ZYNQ GEM: Can't get base address\n");
|
|
|
- return -1;
|
|
|
- }
|
|
|
- }
|
|
|
- } while (offset != -1);
|
|
|
+ const char *phy_mode;
|
|
|
+
|
|
|
+ pdata->iobase = (phys_addr_t)dev_get_addr(dev);
|
|
|
+ priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
|
|
|
+ /* Hardcode for now */
|
|
|
+ priv->emio = 0;
|
|
|
+
|
|
|
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
|
|
|
+ "phy-handle");
|
|
|
+ if (offset > 0)
|
|
|
+ priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
|
|
|
+
|
|
|
+ phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
|
|
|
+ if (phy_mode)
|
|
|
+ pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
|
+ if (pdata->phy_interface == -1) {
|
|
|
+ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ priv->interface = pdata->phy_interface;
|
|
|
|
|
|
- return ret;
|
|
|
+ printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
|
|
|
+ priv->phyaddr, phy_string_for_interface(priv->interface));
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
-#endif
|
|
|
+
|
|
|
+static const struct udevice_id zynq_gem_ids[] = {
|
|
|
+ { .compatible = "cdns,zynqmp-gem" },
|
|
|
+ { .compatible = "cdns,zynq-gem" },
|
|
|
+ { .compatible = "cdns,gem" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(zynq_gem) = {
|
|
|
+ .name = "zynq_gem",
|
|
|
+ .id = UCLASS_ETH,
|
|
|
+ .of_match = zynq_gem_ids,
|
|
|
+ .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
|
|
|
+ .probe = zynq_gem_probe,
|
|
|
+ .remove = zynq_gem_remove,
|
|
|
+ .ops = &zynq_gem_ops,
|
|
|
+ .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
|
+};
|
Tom Rini