davinci: omapl138_lcdk: fix PLL0 frequency

commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).

So here is what we have currently:

PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec)
         ^     ^         ^
       CLKIN PREDIV    PLLM (out of spec)

input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

This changes the PLLM value to 18 and the POSTDIV value to 0 so that
PLLOUT is now within specification but we still get the desired
result.

PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec)
         ^     ^         ^
       CLKIN PREDIV     PLLM

input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

Fixes: 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency")
Signed-off-by: David Lechner <david@lechnology.com>
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>

configs/omapl138_lcdk_defconfig

@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_SYS_TEXT_BASE=0xc1080000
 CONFIG_TARGET_OMAPL138_LCDK=y
+CONFIG_SYS_DA850_PLL0_POSTDIV=0
 CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

include/configs/omapl138_lcdk.h

@@ -57,7 +57,8 @@
  * PLL configuration
  */
 
-#define CONFIG_SYS_DA850_PLL0_PLLM     37
+/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
+#define CONFIG_SYS_DA850_PLL0_PLLM     18
 #define CONFIG_SYS_DA850_PLL1_PLLM     21
 
 /*