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@@ -25,12 +25,6 @@ struct flow_ctlr {
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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- u32 flow_dbg_sel; /* offset 0x44 */
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- u32 flow_dbg_cnt0; /* offset 0x48 */
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- u32 flow_dbg_cnt1; /* offset 0x4c */
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- u32 flow_dbg_qual; /* offset 0x50 */
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- u32 flow_ctlr_spare; /* offset 0x54 */
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- u32 ram_repair_cluster1;/* offset 0x58 */
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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@@ -48,10 +42,4 @@ struct flow_ctlr {
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#define CSR_WAIT_WFI_SHIFT 8
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#define CSR_PWR_OFF_STS (1 << 16)
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-/* RAM_REPAIR, 0x40, 0x58 */
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-enum {
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- RAM_REPAIR_REQ = 0x1 << 0,
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- RAM_REPAIR_STS = 0x1 << 1,
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-};
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-
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#endif /* _TEGRA124_FLOW_H_ */
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